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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos3250.dtsi58 clocks = <&cmu CLK_ARM_CLK>;
81 clocks = <&cmu CLK_ARM_CLK>;
168 clocks = <&cmu CLK_FIN_PLL>;
213 cmu: clock-controller@10030000 { label
214 compatible = "samsung,exynos3250-cmu";
217 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
218 <&cmu CLK_MOUT_ACLK_266_SUB>;
219 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
220 <&cmu CLK_FIN_PLL>;
224 compatible = "samsung,exynos3250-cmu-dmc";
[all …]
H A Defm32gg.dtsi10 #include "dt-bindings/clock/efm32-cmu.h"
34 clocks = <&cmu clk_HFPERCLKADC0>;
46 clocks = <&cmu clk_HFPERCLKGPIO>;
56 clocks = <&cmu clk_HFPERCLKI2C0>;
67 clocks = <&cmu clk_HFPERCLKI2C1>;
78 clocks = <&cmu clk_HFPERCLKUSART0>;
88 clocks = <&cmu clk_HFPERCLKUSART1>;
98 clocks = <&cmu clk_HFPERCLKUSART2>;
106 clocks = <&cmu clk_HFPERCLKUSART0>;
114 clocks = <&cmu clk_HFPERCLKUSART1>;
[all …]
H A Dexynos3250-artik5.dtsi54 assigned-clocks = <&cmu CLK_SCLK_TSADC>;
58 &cmu {
398 clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
404 assigned-clocks = <&cmu CLK_SCLK_UART0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dexynos5433-clock.txt1 * Samsung Exynos5433 CMU (Clock Management Units)
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
H A Dactions,owl-cmu.txt1 * Actions Semi Owl Clock Management Unit (CMU)
10 "actions,s900-cmu"
11 "actions,s700-cmu"
12 "actions,s500-cmu"
23 dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
24 actions,s500-cmu.h header and can be used in device tree sources.
31 Actions Semi S900 CMU also requires one more clock:
36 cmu: clock-controller@e0160000 {
37 compatible = "actions,s900-cmu";
51 clocks = <&cmu CLK_UART5>;
H A Dexynos3250-clock.txt9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10 - "samsung,exynos3250-cmu-dmc" - controller compatible with
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
29 cmu: clock-controller@10030000 {
30 compatible = "samsung,exynos3250-cmu";
36 compatible = "samsung,exynos3250-cmu-dmc";
42 compatible = "samsung,exynos3250-cmu-isp";
55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
H A Defm32-clock.txt4 - compatible: Should be "efm32gg,cmu"
6 - interrupts: Interrupt used by the CMU
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/actions/
H A Ds900.dtsi6 #include <dt-bindings/clock/actions,s900-cmu.h>
125 clocks = <&cmu CLK_UART0>;
133 clocks = <&cmu CLK_UART1>;
141 clocks = <&cmu CLK_UART2>;
149 clocks = <&cmu CLK_UART3>;
157 clocks = <&cmu CLK_UART4>;
165 clocks = <&cmu CLK_UART5>;
173 clocks = <&cmu CLK_UART6>;
184 cmu: clock-controller@e0160000 { label
185 compatible = "actions,s900-cmu";
[all …]
H A Ds700.dtsi6 #include <dt-bindings/clock/actions,s700-cmu.h>
119 clocks = <&cmu CLK_UART0>;
127 clocks = <&cmu CLK_UART1>;
135 clocks = <&cmu CLK_UART2>;
143 clocks = <&cmu CLK_UART3>;
151 clocks = <&cmu CLK_UART4>;
159 clocks = <&cmu CLK_UART5>;
167 clocks = <&cmu CLK_UART6>;
172 cmu: clock-controller@e0168000 { label
173 compatible = "actions,s700-cmu";
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk.c343 * for each CMU. It also add CMU register list to register cache.
347 const struct samsung_cmu_info *cmu) in samsung_cmu_register_one() argument
358 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); in samsung_cmu_register_one()
360 if (cmu->pll_clks) in samsung_cmu_register_one()
361 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, in samsung_cmu_register_one()
363 if (cmu->mux_clks) in samsung_cmu_register_one()
364 samsung_clk_register_mux(ctx, cmu->mux_clks, in samsung_cmu_register_one()
365 cmu->nr_mux_clks); in samsung_cmu_register_one()
366 if (cmu->div_clks) in samsung_cmu_register_one()
367 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks); in samsung_cmu_register_one()
[all …]
H A Dclk-exynos5-subcmu.c17 static const struct exynos5_subcmu_info **cmu; variable
48 * Pass the needed clock provider context and register sub-CMU clocks
62 cmu = _cmu; in exynos5_subcmus_init()
166 if (strcmp(cmu[i]->pd_name, name) == 0) in exynos5_clk_probe()
168 cmu[i], np); in exynos5_clk_probe()
/OK3568_Linux_fs/u-boot/drivers/clk/exynos/
H A Dclk-exynos7420.c22 /* CMU TOPC block device structure */
34 /* CMU TOP0 block device structure */
43 * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
45 * @topc: base address of the memory mapped CMU TOPC controller.
58 * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
60 * @top0: base address of the memory mapped CMU TOP0 controller.
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dexynos3250.h22 * Main CMU
260 * Total number of clocks of main CMU.
266 * CMU DMC
287 * Total number of clocks of main CMU.
293 * CMU ISP
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/devfreq/
H A Dexynos-bus.txt227 clocks = <&cmu CLK_DIV_GDL>;
235 clocks = <&cmu CLK_DIV_GDR>;
243 clocks = <&cmu CLK_DIV_ACLK_160>;
251 clocks = <&cmu CLK_DIV_ACLK_200>;
259 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
267 clocks = <&cmu CLK_DIV_ACLK_266>;
275 clocks = <&cmu CLK_DIV_ACLK_100>;
283 clocks = <&cmu CLK_SCLK_MFC>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi271 compatible = "samsung,exynos5433-cmu-top";
286 compatible = "samsung,exynos5433-cmu-cpif";
295 compatible = "samsung,exynos5433-cmu-mif";
306 compatible = "samsung,exynos5433-cmu-peric";
312 compatible = "samsung,exynos5433-cmu-peris";
318 compatible = "samsung,exynos5433-cmu-fsys";
345 compatible = "samsung,exynos5433-cmu-g2d";
359 compatible = "samsung,exynos5433-cmu-disp";
385 compatible = "samsung,exynos5433-cmu-aud";
394 compatible = "samsung,exynos5433-cmu-bus0";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.txt25 SERDES. Should have 3 items for CMU reference clock,
53 first refers to the CMU reference clock, second refers to the left output
58 CMU reference clock to left input reference clock.
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-efm32gg.c12 #include <dt-bindings/clock/efm32-cmu.h>
38 pr_warn("Failed to map address range for efm32gg,cmu node\n"); in efm32gg_cmu_init()
84 CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
/OK3568_Linux_fs/yocto/meta-openembedded/meta-python/recipes-devtools/python/
H A Dpython3-pocketsphinx_0.1.15.bb1 SUMMARY = "This package provides a python interface to CMU Sphinxbase and Pocketsphinx libraries cr…
2 DESCRIPTION = "Python interface to CMU Sphinxbase and Pocketsphinx libraries"
/OK3568_Linux_fs/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c45 struct serdes_cfg cmu[SERDES_CMU_CFG_NUM]; member
70 .cmu = {
131 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); in ks2_serdes_init_cfg()
147 /* Enable CMU and COMLANE */ in ks2_serdes_cmu_comlane_enable()
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/44x/
H A Dfsp2.c32 #define FSP2_CMU_ERR "ibm,cmu-error-irq"
132 pr_err("CMU Error\n"); in cmu_err_handler()
134 panic("CMU Error\n"); in cmu_err_handler()
260 * recorded in the CMU FIR and leading to erroneous interrupt requests in fsp2_probe()
261 * once the CMU interrupt is unmasked. in fsp2_probe()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dowl-mmc.yaml58 clocks = <&cmu 56>;
59 resets = <&cmu 23>;
/OK3568_Linux_fs/yocto/poky/meta/files/common-licenses/
H A DNet-SNMP1 ---- Part 1: CMU/UCD copyright notice: (BSD like) -----
9 …permission notice appear in supporting documentation, and that the name of CMU and The Regents of …
11 CMU AND THE REGENTS OF THE UNIVERSITY OF CALIFORNIA DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOF…
/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-xgene.c10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
[all …]
/OK3568_Linux_fs/kernel/fs/coda/
H A Dcache.c8 * to the Coda project http://www.coda.cs.cmu.edu/ <coda@cs.cmu.edu>.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml161 clocks = <&cmu CLK_TSADC>,
162 <&cmu CLK_SCLK_TSADC>;

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