1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 Pengutronix
4*4882a593Smuzhiyun * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <dt-bindings/clock/efm32-cmu.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define CMU_HFPERCLKEN0 0x44
15*4882a593Smuzhiyun #define CMU_MAX_CLKS 37
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static struct clk_hw_onecell_data *clk_data;
18*4882a593Smuzhiyun
efm32gg_cmu_init(struct device_node * np)19*4882a593Smuzhiyun static void __init efm32gg_cmu_init(struct device_node *np)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun int i;
22*4882a593Smuzhiyun void __iomem *base;
23*4882a593Smuzhiyun struct clk_hw **hws;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS),
26*4882a593Smuzhiyun GFP_KERNEL);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (!clk_data)
29*4882a593Smuzhiyun return;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun hws = clk_data->hws;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun for (i = 0; i < CMU_MAX_CLKS; ++i)
34*4882a593Smuzhiyun hws[i] = ERR_PTR(-ENOENT);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun base = of_iomap(np, 0);
37*4882a593Smuzhiyun if (!base) {
38*4882a593Smuzhiyun pr_warn("Failed to map address range for efm32gg,cmu node\n");
39*4882a593Smuzhiyun return;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
43*4882a593Smuzhiyun 48000000);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
46*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
47*4882a593Smuzhiyun hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
48*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
49*4882a593Smuzhiyun hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
50*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
51*4882a593Smuzhiyun hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
52*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
53*4882a593Smuzhiyun hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
54*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
55*4882a593Smuzhiyun hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
56*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
57*4882a593Smuzhiyun hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
58*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
59*4882a593Smuzhiyun hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
60*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
61*4882a593Smuzhiyun hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
62*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
63*4882a593Smuzhiyun hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
64*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
65*4882a593Smuzhiyun hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
66*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
67*4882a593Smuzhiyun hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
68*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
69*4882a593Smuzhiyun hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
70*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
71*4882a593Smuzhiyun hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
72*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
73*4882a593Smuzhiyun hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
74*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
75*4882a593Smuzhiyun hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
76*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
77*4882a593Smuzhiyun hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
78*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
79*4882a593Smuzhiyun hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
80*4882a593Smuzhiyun "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
85