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/OK3568_Linux_fs/kernel/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
43 * struct clk_rate_request - Structure encoding the clk constraints that
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/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
49 * @name: Parent name
50 * @id: Parent clock ID
54 char name[MAX_NAME_LEN]; member
60 * struct zynqmp_clock - Clock
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H A Dclk-gate-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Gated clock implementation
10 #include <linux/clk-provider.h>
12 #include "clk-zynqmp.h"
15 * struct clk_gate - gating clock
16 * @hw: handle between common and hardware-specific interfaces
17 * @flags: hardware-specific flags
18 * @clk_id: Id of clock
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/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Common Clock Framework support for all Samsung platforms
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
17 * struct samsung_clk_provider: information about clock provider
19 * @lock: maintains exclusion between callbacks for a given clock-provider.
20 * @clk_data: holds clock related data like clk_hw* and number of clocks.
31 * struct samsung_clock_alias: information about mux clock
32 * @id: platform specific id of the clock.
33 * @dev_name: name of the device to which this clock belongs.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
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H A Dexynos4210-trats.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
30 stdout-path = "serial2:115200n8";
33 vemmc_reg: regulator-0 {
34 compatible = "regulator-fixed";
35 regulator-name = "VMEM_VDD_2.8V";
36 regulator-min-microvolt = <2800000>;
37 regulator-max-microvolt = <2800000>;
39 enable-active-high;
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H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
28 stdout-path = "serial2:115200n8";
32 fixed-rate-clocks {
34 compatible = "samsung,clock-xxti";
35 clock-frequency = <0>;
39 compatible = "samsung,clock-xusbxti";
40 clock-frequency = <24000000>;
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H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
28 stdout-path = "serial2:115200n8";
31 vemmc_reg: regulator-0 {
32 compatible = "regulator-fixed";
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/OK3568_Linux_fs/kernel/drivers/isdn/mISDN/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
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/OK3568_Linux_fs/external/mpp/osal/
H A Dmpp_time.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
55 RK_S64 diff = end - start; in mpp_time_diff()
62 char name[16]; member
72 MPP_RET check_is_mpp_clock(void *clock) in check_is_mpp_clock() argument
74 if (clock && ((MppClockImpl*)clock)->check == clock_name) in check_is_mpp_clock()
77 mpp_err_f("pointer %p failed on check\n", clock); in check_is_mpp_clock()
82 MppClock mpp_clock_get(const char *name) in mpp_clock_get() argument
86 impl->check = clock_name; in mpp_clock_get()
87 snprintf(impl->name, sizeof(impl->name) - 1, name, NULL); in mpp_clock_get()
94 void mpp_clock_put(MppClock clock) in mpp_clock_put() argument
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/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dclk-mstp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * status register when enabling the clock.
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
37 * @width_8bit: registers are 8-bit, not 32-bit
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
66 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
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H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
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H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
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/OK3568_Linux_fs/external/mpp/osal/inc/
H A Dmpp_time.h8 * http://www.apache.org/licenses/LICENSE-2.0
44 * Clock create / destroy / enable / disable function
45 * Note when clock is create it is default disabled user need to call enable
46 * fucntion with enable = 1 to enable the clock.
47 * User can use enable function with enable = 0 to disable the clock.
49 MppClock mpp_clock_get(const char *name);
50 void mpp_clock_put(MppClock clock);
51 void mpp_clock_enable(MppClock clock, RK_U32 enable);
54 * Clock basic operation function:
55 * start : let clock start timing counter
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/OK3568_Linux_fs/kernel/drivers/clk/uniphier/
H A Dclk-uniphier-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
14 #include "clk-uniphier.h"
20 switch (data->type) { in uniphier_clk_register()
22 return uniphier_clk_register_cpugear(dev, regmap, data->name, in uniphier_clk_register()
23 &data->data.cpugear); in uniphier_clk_register()
25 return uniphier_clk_register_fixed_factor(dev, data->name, in uniphier_clk_register()
26 &data->data.factor); in uniphier_clk_register()
28 return uniphier_clk_register_fixed_rate(dev, data->name, in uniphier_clk_register()
29 &data->data.rate); in uniphier_clk_register()
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/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Dadpll.c14 #include <linux/clk-provider.h>
186 const char *name; in ti_adpll_clk_get_name() local
190 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
191 "clock-output-names", in ti_adpll_clk_get_name()
193 &name); in ti_adpll_clk_get_name()
197 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
198 d->pa, postfix); in ti_adpll_clk_get_name()
201 return name; in ti_adpll_clk_get_name()
206 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
207 int index, int output_index, const char *name, in ti_adpll_setup_clock() argument
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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
37 #include <dt-bindings/clock/bcm2835.h>
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
300 * with an external parent's name. This array is in the order that
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H A Dclk-bcm63xx-gate.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/bcm3368-clock.h>
10 #include <dt-bindings/clock/bcm6318-clock.h>
11 #include <dt-bindings/clock/bcm6328-clock.h>
12 #include <dt-bindings/clock/bcm6358-clock.h>
13 #include <dt-bindings/clock/bcm6362-clock.h>
14 #include <dt-bindings/clock/bcm6368-clock.h>
15 #include <dt-bindings/clock/bcm63268-clock.h>
18 const char * const name; member
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H A Dclk-kona-setup.c18 #include "clk-kona.h"
21 #define selector_clear_exists(sel) ((sel)->width = 0)
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
34 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
40 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
53 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
57 if (bcm_clk->type != bcm_clk_peri) in clk_requires_trigger()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3368-sziauto-rk618.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rk3368-android.dtsi"
10 #include <dt-bindings/pwm/pwm.h>
11 #include <dt-bindings/clock/rk618-cru.h>
18 compatible = "simple-panel";
20 enable-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
21 prepare-delay-ms = <20>;
22 enable-delay-ms = <20>;
23 disable-delay-ms = <20>;
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
9 * bcm235xx architecture clock framework
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
77 /* Enable a peripheral clock */
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
9 * bcm281xx architecture clock framework
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
77 /* Enable a peripheral clock */
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
52 const char *name; member
57 const char *name; member
115 if (!core->rpm_enabled) in clk_pm_runtime_get()
118 ret = pm_runtime_get_sync(core->dev); in clk_pm_runtime_get()
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