xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3368-sziauto-rk618.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include "rk3368.dtsi"
9*4882a593Smuzhiyun#include "rk3368-android.dtsi"
10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
11*4882a593Smuzhiyun#include <dt-bindings/clock/rk618-cru.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	model = "Rockchip rk3368 Sziauto board";
15*4882a593Smuzhiyun	compatible = "rockchip,sziauto", "rockchip,rk3368";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	panel {
18*4882a593Smuzhiyun		compatible = "simple-panel";
19*4882a593Smuzhiyun		backlight = <&backlight>;
20*4882a593Smuzhiyun		enable-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
21*4882a593Smuzhiyun		prepare-delay-ms = <20>;
22*4882a593Smuzhiyun		enable-delay-ms = <20>;
23*4882a593Smuzhiyun		disable-delay-ms = <20>;
24*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
25*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		display-timings {
28*4882a593Smuzhiyun			native-mode = <&timing0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun			timing0: timing0 {
31*4882a593Smuzhiyun				clock-frequency = <136000000>;
32*4882a593Smuzhiyun				hactive = <1920>;
33*4882a593Smuzhiyun				vactive = <1080>;
34*4882a593Smuzhiyun				hback-porch = <60>;
35*4882a593Smuzhiyun				hfront-porch = <60>;
36*4882a593Smuzhiyun				hsync-len = <40>;
37*4882a593Smuzhiyun				vback-porch = <4>;
38*4882a593Smuzhiyun				vfront-porch = <4>;
39*4882a593Smuzhiyun				vsync-len = <3>;
40*4882a593Smuzhiyun				hsync-active = <0>;
41*4882a593Smuzhiyun				vsync-active = <0>;
42*4882a593Smuzhiyun				de-active = <0>;
43*4882a593Smuzhiyun				pixelclk-active = <0>;
44*4882a593Smuzhiyun			};
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		port {
48*4882a593Smuzhiyun			panel_in_lvds: endpoint {
49*4882a593Smuzhiyun				remote-endpoint = <&lvds_out_panel>;
50*4882a593Smuzhiyun			};
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
55*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
56*4882a593Smuzhiyun		clocks = <&rk818 1>;
57*4882a593Smuzhiyun		clock-names = "ext_clock";
58*4882a593Smuzhiyun		pinctrl-names = "default";
59*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		/*
62*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
63*4882a593Smuzhiyun		 * on the actual card populated):
64*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
65*4882a593Smuzhiyun		 * - PDN (power down when low)
66*4882a593Smuzhiyun		 */
67*4882a593Smuzhiyun		 reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	backlight: backlight {
71*4882a593Smuzhiyun		compatible = "pwm-backlight";
72*4882a593Smuzhiyun		pwms = <&pwm0 0 50000 0>;
73*4882a593Smuzhiyun		brightness-levels = <
74*4882a593Smuzhiyun			 32  32  34  34  36  36  38  38  40  40
75*4882a593Smuzhiyun			 42  42  44  44  46  46  48  48  50  50
76*4882a593Smuzhiyun			 52  52  54  54  56  56  58  58  60  60
77*4882a593Smuzhiyun			 62  62  64  64  66  66  68  68  70  70
78*4882a593Smuzhiyun			 72  72  74  74  76  76  78  78  80  80
79*4882a593Smuzhiyun			 82  82  84  84  86  86  88  88  90  90
80*4882a593Smuzhiyun			 92  92  94  94  96  96  98  98 100 100
81*4882a593Smuzhiyun			102 102 104 104 106 106 108 108 110 110
82*4882a593Smuzhiyun			112 112 114 114 116 116 118 118 120 120
83*4882a593Smuzhiyun			122 122 124 124 126 126 128 128 130 130
84*4882a593Smuzhiyun			132 132 134 134 136 136 138 138 140 140
85*4882a593Smuzhiyun			142 142 144 144 146 146 148 148 150 150
86*4882a593Smuzhiyun			152 152 154 154 156 156 158 158 160 160
87*4882a593Smuzhiyun			162 162 164 164 166 166 168 168 170 170
88*4882a593Smuzhiyun			172 172 174 174 176 176 178 178 180 180
89*4882a593Smuzhiyun			182 182 184 184 186 186 188 188 190 190
90*4882a593Smuzhiyun			192 192 194 194 196 196 198 198 200 200
91*4882a593Smuzhiyun			202 202 204 204 206 206 208 208 210 210
92*4882a593Smuzhiyun			212 212 214 214 216 216 218 218 220 220
93*4882a593Smuzhiyun			222 222 224 224 225 225 226 226 227 227
94*4882a593Smuzhiyun			228 228 229 229 230 230 231 231 232 232
95*4882a593Smuzhiyun			233 233 234 234 235 235 236 236 237 237
96*4882a593Smuzhiyun			238 238 239 239 240 240 241 241 242 242
97*4882a593Smuzhiyun			243 243 244 244 245 245 246 246 247 247
98*4882a593Smuzhiyun			248 248 249 249 250 250 251 251 252 252
99*4882a593Smuzhiyun			253 253 254 254 255 255>;
100*4882a593Smuzhiyun		default-brightness-level = <120>;
101*4882a593Smuzhiyun		enable-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	rockchip-key {
105*4882a593Smuzhiyun		compatible = "rockchip,key";
106*4882a593Smuzhiyun		io-channels = <&saradc 1>;
107*4882a593Smuzhiyun		status = "okay";
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		vol-up-key {
110*4882a593Smuzhiyun			linux,code = <115>;
111*4882a593Smuzhiyun			label = "volume up";
112*4882a593Smuzhiyun			rockchip,adc_value = <1>;
113*4882a593Smuzhiyun		};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		vol-down-key {
116*4882a593Smuzhiyun			linux,code = <114>;
117*4882a593Smuzhiyun			label = "volume down";
118*4882a593Smuzhiyun			rockchip,adc_value = <170>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		power-key {
122*4882a593Smuzhiyun			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
123*4882a593Smuzhiyun			linux,code = <116>;
124*4882a593Smuzhiyun			label = "power";
125*4882a593Smuzhiyun			gpio-key,wakeup;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		menu-key {
129*4882a593Smuzhiyun			linux,code = <59>;
130*4882a593Smuzhiyun			label = "menu";
131*4882a593Smuzhiyun			rockchip,adc_value = <355>;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		home-key {
135*4882a593Smuzhiyun			linux,code = <102>;
136*4882a593Smuzhiyun			label = "home";
137*4882a593Smuzhiyun			rockchip,adc_value = <746>;
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		back-key {
141*4882a593Smuzhiyun			linux,code = <158>;
142*4882a593Smuzhiyun			label = "back";
143*4882a593Smuzhiyun			rockchip,adc_value = <560>;
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun		camera-key {
147*4882a593Smuzhiyun			linux,code = <212>;
148*4882a593Smuzhiyun			label = "camera";
149*4882a593Smuzhiyun			rockchip,adc_value = <450>;
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	vcc_sys: vcc-sys {
154*4882a593Smuzhiyun		compatible = "regulator-fixed";
155*4882a593Smuzhiyun		regulator-name = "vcc_sys";
156*4882a593Smuzhiyun		regulator-always-on;
157*4882a593Smuzhiyun		regulator-boot-on;
158*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
159*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	vcc_host: vcc-host {
163*4882a593Smuzhiyun		compatible = "regulator-fixed";
164*4882a593Smuzhiyun		enable-active-high;
165*4882a593Smuzhiyun		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
166*4882a593Smuzhiyun		pinctrl-names = "default";
167*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
168*4882a593Smuzhiyun		regulator-name = "vcc_host";
169*4882a593Smuzhiyun		regulator-always-on;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	xin32k: xin32k {
173*4882a593Smuzhiyun		compatible = "fixed-clock";
174*4882a593Smuzhiyun		clock-frequency = <32768>;
175*4882a593Smuzhiyun		clock-output-names = "xin32k";
176*4882a593Smuzhiyun		#clock-cells = <0>;
177*4882a593Smuzhiyun	};
178*4882a593Smuzhiyun};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun&firmware_android {
181*4882a593Smuzhiyun	compatible = "android,firmware";
182*4882a593Smuzhiyun	fstab {
183*4882a593Smuzhiyun		compatible = "android,fstab";
184*4882a593Smuzhiyun		system {
185*4882a593Smuzhiyun			compatible = "android,system";
186*4882a593Smuzhiyun			dev = "/dev/block/by-name/system";
187*4882a593Smuzhiyun			type = "ext4";
188*4882a593Smuzhiyun			mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
189*4882a593Smuzhiyun			fsmgr_flags = "wait,verify";
190*4882a593Smuzhiyun		};
191*4882a593Smuzhiyun		vendor {
192*4882a593Smuzhiyun			compatible = "android,vendor";
193*4882a593Smuzhiyun			dev = "/dev/block/by-name/vendor";
194*4882a593Smuzhiyun			type = "ext4";
195*4882a593Smuzhiyun			mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
196*4882a593Smuzhiyun			fsmgr_flags = "wait,verify";
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&i2c5 {
202*4882a593Smuzhiyun	status = "okay";
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	rk618@50 {
205*4882a593Smuzhiyun		compatible = "rockchip,rk618";
206*4882a593Smuzhiyun		reg = <0x50>;
207*4882a593Smuzhiyun		pinctrl-names = "default";
208*4882a593Smuzhiyun		pinctrl-0 = <&i2s_8ch_mclk>;
209*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S_8CH_OUT>;
210*4882a593Smuzhiyun		clock-names = "clkin";
211*4882a593Smuzhiyun		assigned-clocks = <&cru SCLK_I2S_8CH_OUT>;
212*4882a593Smuzhiyun		assigned-clock-rates = <11289600>;
213*4882a593Smuzhiyun		reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
214*4882a593Smuzhiyun		status = "okay";
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun		clock: cru {
217*4882a593Smuzhiyun			compatible = "rockchip,rk618-cru";
218*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>;
219*4882a593Smuzhiyun			clock-names = "clkin", "lcdc0_dclkp";
220*4882a593Smuzhiyun			assigned-clocks = <&clock SCALER_PLLIN_CLK>, <&clock VIF_PLLIN_CLK>,
221*4882a593Smuzhiyun					  <&clock SCALER_CLK>, <&clock VIF0_PRE_CLK>,
222*4882a593Smuzhiyun					  <&clock CODEC_CLK>, <&clock DITHER_CLK>;
223*4882a593Smuzhiyun			assigned-clock-parents = <&cru SCLK_I2S_8CH_OUT>, <&clock LCDC0_CLK>,
224*4882a593Smuzhiyun						 <&clock SCALER_PLL_CLK>, <&clock VIF_PLL_CLK>,
225*4882a593Smuzhiyun						 <&cru SCLK_I2S_8CH_OUT>, <&clock VIF0_CLK>;
226*4882a593Smuzhiyun			#clock-cells = <1>;
227*4882a593Smuzhiyun			status = "okay";
228*4882a593Smuzhiyun		};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun		hdmi {
231*4882a593Smuzhiyun			compatible = "rockchip,rk618-hdmi";
232*4882a593Smuzhiyun			clocks = <&clock HDMI_CLK>;
233*4882a593Smuzhiyun			clock-names = "hdmi";
234*4882a593Smuzhiyun			assigned-clocks = <&clock HDMI_CLK>;
235*4882a593Smuzhiyun			assigned-clock-parents = <&clock VIF0_CLK>;
236*4882a593Smuzhiyun			interrupt-parent = <&gpio3>;
237*4882a593Smuzhiyun			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
238*4882a593Smuzhiyun			status = "okay";
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			ports {
241*4882a593Smuzhiyun				#address-cells = <1>;
242*4882a593Smuzhiyun				#size-cells = <0>;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun				port@0 {
245*4882a593Smuzhiyun					reg = <0>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun					hdmi_in_vif: endpoint {
248*4882a593Smuzhiyun						remote-endpoint = <&vif_out_hdmi>;
249*4882a593Smuzhiyun					};
250*4882a593Smuzhiyun				};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun				port@1 {
253*4882a593Smuzhiyun					reg = <1>;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun					hdmi_out_scaler: endpoint {
256*4882a593Smuzhiyun						remote-endpoint = <&scaler_in_hdmi>;
257*4882a593Smuzhiyun					};
258*4882a593Smuzhiyun				};
259*4882a593Smuzhiyun			};
260*4882a593Smuzhiyun		};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun		lvds {
263*4882a593Smuzhiyun			compatible = "rockchip,rk618-lvds";
264*4882a593Smuzhiyun			clocks = <&clock LVDS_CLK>;
265*4882a593Smuzhiyun			clock-names = "lvds";
266*4882a593Smuzhiyun			dual-channel;
267*4882a593Smuzhiyun			status = "okay";
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun			ports {
270*4882a593Smuzhiyun				#address-cells = <1>;
271*4882a593Smuzhiyun				#size-cells = <0>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun				port@0 {
274*4882a593Smuzhiyun					reg = <0>;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun					lvds_in_scaler: endpoint {
277*4882a593Smuzhiyun						remote-endpoint = <&scaler_out_lvds>;
278*4882a593Smuzhiyun					};
279*4882a593Smuzhiyun				};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun				port@1 {
282*4882a593Smuzhiyun					reg = <1>;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun					lvds_out_panel: endpoint {
285*4882a593Smuzhiyun						remote-endpoint = <&panel_in_lvds>;
286*4882a593Smuzhiyun					};
287*4882a593Smuzhiyun				};
288*4882a593Smuzhiyun			};
289*4882a593Smuzhiyun		};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun		scaler {
292*4882a593Smuzhiyun			compatible = "rockchip,rk618-scaler";
293*4882a593Smuzhiyun			clocks = <&clock SCALER_CLK>, <&clock VIF0_CLK>,
294*4882a593Smuzhiyun				 <&clock DITHER_CLK>;
295*4882a593Smuzhiyun			clock-names = "scaler", "vif", "dither";
296*4882a593Smuzhiyun			status = "okay";
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun			ports {
299*4882a593Smuzhiyun				#address-cells = <1>;
300*4882a593Smuzhiyun				#size-cells = <0>;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun				port@0 {
303*4882a593Smuzhiyun					reg = <0>;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun					scaler_in_hdmi: endpoint {
306*4882a593Smuzhiyun						remote-endpoint = <&hdmi_out_scaler>;
307*4882a593Smuzhiyun					};
308*4882a593Smuzhiyun				};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun				port@1 {
311*4882a593Smuzhiyun					reg = <1>;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun					scaler_out_lvds: endpoint {
314*4882a593Smuzhiyun						remote-endpoint = <&lvds_in_scaler>;
315*4882a593Smuzhiyun					};
316*4882a593Smuzhiyun				};
317*4882a593Smuzhiyun			};
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		vif {
321*4882a593Smuzhiyun			compatible = "rockchip,rk618-vif";
322*4882a593Smuzhiyun			clocks = <&clock VIF0_CLK>, <&clock VIF0_PRE_CLK>;
323*4882a593Smuzhiyun			clock-names = "vif", "vif_pre";
324*4882a593Smuzhiyun			status = "okay";
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun			ports {
327*4882a593Smuzhiyun				#address-cells = <1>;
328*4882a593Smuzhiyun				#size-cells = <0>;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun				port@0 {
331*4882a593Smuzhiyun					reg = <0>;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun					vif_in_rgb: endpoint {
334*4882a593Smuzhiyun						remote-endpoint = <&rgb_out_vif>;
335*4882a593Smuzhiyun					};
336*4882a593Smuzhiyun				};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun				port@1 {
339*4882a593Smuzhiyun					reg = <1>;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun					vif_out_hdmi: endpoint {
342*4882a593Smuzhiyun						remote-endpoint = <&hdmi_in_vif>;
343*4882a593Smuzhiyun					};
344*4882a593Smuzhiyun				};
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun	};
348*4882a593Smuzhiyun};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun&rgb {
351*4882a593Smuzhiyun	status = "okay";
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun	ports {
354*4882a593Smuzhiyun		port@1 {
355*4882a593Smuzhiyun			reg = <1>;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun			rgb_out_vif: endpoint {
358*4882a593Smuzhiyun				remote-endpoint = <&vif_in_rgb>;
359*4882a593Smuzhiyun			};
360*4882a593Smuzhiyun		};
361*4882a593Smuzhiyun	};
362*4882a593Smuzhiyun};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun&route_rgb {
365*4882a593Smuzhiyun	status = "okay";
366*4882a593Smuzhiyun};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun&emmc {
369*4882a593Smuzhiyun	status = "okay";
370*4882a593Smuzhiyun	bus-width = <8>;
371*4882a593Smuzhiyun	cap-mmc-highspeed;
372*4882a593Smuzhiyun	mmc-hs200-1_8v;
373*4882a593Smuzhiyun	no-sdio;
374*4882a593Smuzhiyun	no-sd;
375*4882a593Smuzhiyun	disable-wp;
376*4882a593Smuzhiyun	non-removable;
377*4882a593Smuzhiyun	num-slots = <1>;
378*4882a593Smuzhiyun	pinctrl-names = "default";
379*4882a593Smuzhiyun	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&sdmmc {
383*4882a593Smuzhiyun	status = "disabled";
384*4882a593Smuzhiyun	clock-frequency = <37500000>;
385*4882a593Smuzhiyun	clock-freq-min-max = <400000 37500000>;
386*4882a593Smuzhiyun	no-sdio;
387*4882a593Smuzhiyun	no-mmc;
388*4882a593Smuzhiyun	cap-mmc-highspeed;
389*4882a593Smuzhiyun	cap-sd-highspeed;
390*4882a593Smuzhiyun	card-detect-delay = <200>;
391*4882a593Smuzhiyun	disable-wp;
392*4882a593Smuzhiyun	num-slots = <1>;
393*4882a593Smuzhiyun	pinctrl-names = "default";
394*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
395*4882a593Smuzhiyun};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun&sdio0 {
398*4882a593Smuzhiyun	clock-frequency = <50000000>;
399*4882a593Smuzhiyun	clock-freq-min-max = <200000 50000000>;
400*4882a593Smuzhiyun	no-sd;
401*4882a593Smuzhiyun	no-mmc;
402*4882a593Smuzhiyun	bus-width = <4>;
403*4882a593Smuzhiyun	disable-wp;
404*4882a593Smuzhiyun	cap-sd-highspeed;
405*4882a593Smuzhiyun	cap-sdio-irq;
406*4882a593Smuzhiyun	keep-power-in-suspend;
407*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
408*4882a593Smuzhiyun	non-removable;
409*4882a593Smuzhiyun	num-slots = <1>;
410*4882a593Smuzhiyun	pinctrl-names = "default";
411*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
412*4882a593Smuzhiyun	sd-uhs-sdr104;
413*4882a593Smuzhiyun	status = "okay";
414*4882a593Smuzhiyun};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun&i2c0 {
417*4882a593Smuzhiyun	status = "okay";
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun	syr827: syr827@40 {
420*4882a593Smuzhiyun		compatible = "silergy,syr827";
421*4882a593Smuzhiyun		reg = <0x40>;
422*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
425*4882a593Smuzhiyun		regulator-name = "vdd_arm";
426*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
427*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
428*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
429*4882a593Smuzhiyun		regulator-always-on;
430*4882a593Smuzhiyun		regulator-boot-on;
431*4882a593Smuzhiyun		regulator-initial-state = <3>;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun		regulator-state-mem {
434*4882a593Smuzhiyun			regulator-off-in-suspend;
435*4882a593Smuzhiyun			regulator-suspend-microvolt = <900000>;
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun	rk818: pmic@1c {
440*4882a593Smuzhiyun		compatible = "rockchip,rk818";
441*4882a593Smuzhiyun		reg = <0x1c>;
442*4882a593Smuzhiyun		clock-output-names = "rk818-clkout1", "wifibt_32kin";
443*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
444*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
445*4882a593Smuzhiyun		pinctrl-names = "default";
446*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
447*4882a593Smuzhiyun		rockchip,system-power-controller;
448*4882a593Smuzhiyun		wakeup-source;
449*4882a593Smuzhiyun		#clock-cells = <1>;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun		vcc1-supply = <&vcc_sys>;
452*4882a593Smuzhiyun		vcc2-supply = <&vcc_sys>;
453*4882a593Smuzhiyun		vcc3-supply = <&vcc_sys>;
454*4882a593Smuzhiyun		vcc4-supply = <&vcc_sys>;
455*4882a593Smuzhiyun		vcc6-supply = <&vcc_sys>;
456*4882a593Smuzhiyun		vcc7-supply = <&vcc_sys>;
457*4882a593Smuzhiyun		vcc8-supply = <&vcc_sys>;
458*4882a593Smuzhiyun		vcc9-supply = <&vcc_io>;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun		regulators {
461*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
462*4882a593Smuzhiyun				regulator-name = "vdd_logic";
463*4882a593Smuzhiyun				regulator-always-on;
464*4882a593Smuzhiyun				regulator-boot-on;
465*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
466*4882a593Smuzhiyun				regulator-max-microvolt = <1450000>;
467*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun				regulator-state-mem {
470*4882a593Smuzhiyun					regulator-on-in-suspend;
471*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
472*4882a593Smuzhiyun				};
473*4882a593Smuzhiyun			};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
476*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
477*4882a593Smuzhiyun				regulator-always-on;
478*4882a593Smuzhiyun				regulator-boot-on;
479*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
480*4882a593Smuzhiyun				regulator-max-microvolt = <1250000>;
481*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun				regulator-state-mem {
484*4882a593Smuzhiyun					regulator-on-in-suspend;
485*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
486*4882a593Smuzhiyun				};
487*4882a593Smuzhiyun			};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
490*4882a593Smuzhiyun				regulator-always-on;
491*4882a593Smuzhiyun				regulator-boot-on;
492*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun				regulator-state-mem {
495*4882a593Smuzhiyun					regulator-on-in-suspend;
496*4882a593Smuzhiyun				};
497*4882a593Smuzhiyun			};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun			vcc_io: DCDC_REG4 {
500*4882a593Smuzhiyun				regulator-always-on;
501*4882a593Smuzhiyun				regulator-boot-on;
502*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
503*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
504*4882a593Smuzhiyun				regulator-name = "vcc_io";
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun				regulator-state-mem {
507*4882a593Smuzhiyun					regulator-on-in-suspend;
508*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
509*4882a593Smuzhiyun				};
510*4882a593Smuzhiyun			};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun			vcca_codec: LDO_REG1 {
513*4882a593Smuzhiyun				regulator-always-on;
514*4882a593Smuzhiyun				regulator-boot-on;
515*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
516*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
517*4882a593Smuzhiyun				regulator-name = "vcca_codec";
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun				regulator-state-mem {
520*4882a593Smuzhiyun					regulator-on-in-suspend;
521*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
522*4882a593Smuzhiyun				};
523*4882a593Smuzhiyun			};
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun			vcc_tp: LDO_REG2 {
526*4882a593Smuzhiyun				regulator-always-on;
527*4882a593Smuzhiyun				regulator-boot-on;
528*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
529*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
530*4882a593Smuzhiyun				regulator-name = "vcc_tp";
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun				regulator-state-mem {
533*4882a593Smuzhiyun					regulator-off-in-suspend;
534*4882a593Smuzhiyun				};
535*4882a593Smuzhiyun			};
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun			vdd_10: LDO_REG3 {
538*4882a593Smuzhiyun				regulator-always-on;
539*4882a593Smuzhiyun				regulator-boot-on;
540*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
541*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
542*4882a593Smuzhiyun				regulator-name = "vdd_10";
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun				regulator-state-mem {
545*4882a593Smuzhiyun					regulator-on-in-suspend;
546*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
547*4882a593Smuzhiyun				};
548*4882a593Smuzhiyun			};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun			vcc18_lcd: LDO_REG4 {
551*4882a593Smuzhiyun				regulator-always-on;
552*4882a593Smuzhiyun				regulator-boot-on;
553*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
554*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
555*4882a593Smuzhiyun				regulator-name = "vcc18_lcd";
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun				regulator-state-mem {
558*4882a593Smuzhiyun					regulator-on-in-suspend;
559*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
560*4882a593Smuzhiyun				};
561*4882a593Smuzhiyun			};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun			vccio_pmu: LDO_REG5 {
564*4882a593Smuzhiyun				regulator-always-on;
565*4882a593Smuzhiyun				regulator-boot-on;
566*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
567*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
568*4882a593Smuzhiyun				regulator-name = "vccio_pmu";
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun				regulator-state-mem {
571*4882a593Smuzhiyun					regulator-on-in-suspend;
572*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
573*4882a593Smuzhiyun				};
574*4882a593Smuzhiyun			};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun			vdd10_lcd: LDO_REG6 {
577*4882a593Smuzhiyun				regulator-always-on;
578*4882a593Smuzhiyun				regulator-boot-on;
579*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
580*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
581*4882a593Smuzhiyun				regulator-name = "vdd10_lcd";
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun				regulator-state-mem {
584*4882a593Smuzhiyun					regulator-on-in-suspend;
585*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
586*4882a593Smuzhiyun				};
587*4882a593Smuzhiyun			};
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun			vcc_18: LDO_REG7 {
590*4882a593Smuzhiyun				regulator-always-on;
591*4882a593Smuzhiyun				regulator-boot-on;
592*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
593*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
594*4882a593Smuzhiyun				regulator-name = "vcc_18";
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun				regulator-state-mem {
597*4882a593Smuzhiyun					regulator-on-in-suspend;
598*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
599*4882a593Smuzhiyun				};
600*4882a593Smuzhiyun			};
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun			vccio_wl: LDO_REG8 {
603*4882a593Smuzhiyun				regulator-always-on;
604*4882a593Smuzhiyun				regulator-boot-on;
605*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
606*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
607*4882a593Smuzhiyun				regulator-name = "vccio_wl";
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun				regulator-state-mem {
610*4882a593Smuzhiyun					regulator-on-in-suspend;
611*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
612*4882a593Smuzhiyun				};
613*4882a593Smuzhiyun			};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun			vccio_sd: LDO_REG9 {
616*4882a593Smuzhiyun				regulator-always-on;
617*4882a593Smuzhiyun				regulator-boot-on;
618*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
619*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
620*4882a593Smuzhiyun				regulator-name = "vccio_sd";
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun				regulator-state-mem {
623*4882a593Smuzhiyun					regulator-on-in-suspend;
624*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
625*4882a593Smuzhiyun				};
626*4882a593Smuzhiyun			};
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun			vcc_sd: SWITCH_REG {
629*4882a593Smuzhiyun				regulator-always-on;
630*4882a593Smuzhiyun				regulator-boot-on;
631*4882a593Smuzhiyun				regulator-name = "vcc_sd";
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun				regulator-state-mem {
634*4882a593Smuzhiyun					regulator-on-in-suspend;
635*4882a593Smuzhiyun				};
636*4882a593Smuzhiyun			};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun			boost_otg: DCDC_BOOST {
639*4882a593Smuzhiyun				regulator-name = "boost_otg";
640*4882a593Smuzhiyun				regulator-always-on;
641*4882a593Smuzhiyun				regulator-boot-on;
642*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
643*4882a593Smuzhiyun				regulator-max-microvolt = <5000000>;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun				regulator-state-mem {
646*4882a593Smuzhiyun					regulator-on-in-suspend;
647*4882a593Smuzhiyun					regulator-suspend-microvolt = <5000000>;
648*4882a593Smuzhiyun				};
649*4882a593Smuzhiyun			};
650*4882a593Smuzhiyun		};
651*4882a593Smuzhiyun	};
652*4882a593Smuzhiyun};
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun&cpu_l0 {
655*4882a593Smuzhiyun	cpu-supply = <&syr827>;
656*4882a593Smuzhiyun};
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun&cpu_l1 {
659*4882a593Smuzhiyun	cpu-supply = <&syr827>;
660*4882a593Smuzhiyun};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun&cpu_l2 {
663*4882a593Smuzhiyun	cpu-supply = <&syr827>;
664*4882a593Smuzhiyun};
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun&cpu_l3 {
667*4882a593Smuzhiyun	cpu-supply = <&syr827>;
668*4882a593Smuzhiyun};
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun&cpu_b0 {
671*4882a593Smuzhiyun	cpu-supply = <&syr827>;
672*4882a593Smuzhiyun};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun&cpu_b1 {
675*4882a593Smuzhiyun	cpu-supply = <&syr827>;
676*4882a593Smuzhiyun};
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun&cpu_b2 {
679*4882a593Smuzhiyun	cpu-supply = <&syr827>;
680*4882a593Smuzhiyun};
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun&cpu_b3 {
683*4882a593Smuzhiyun	cpu-supply = <&syr827>;
684*4882a593Smuzhiyun};
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun&gpu {
687*4882a593Smuzhiyun	logic-supply = <&vdd_logic>;
688*4882a593Smuzhiyun};
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun&io_domains {
691*4882a593Smuzhiyun	dvp-supply = <&vcc_18>;
692*4882a593Smuzhiyun	audio-supply = <&vcc_io>;
693*4882a593Smuzhiyun	gpio30-supply = <&vcc_io>;
694*4882a593Smuzhiyun	gpio1830-supply = <&vcc_io>;
695*4882a593Smuzhiyun	sdcard-supply = <&vccio_sd>;
696*4882a593Smuzhiyun	wifi-supply = <&vccio_wl>;
697*4882a593Smuzhiyun	status = "okay";
698*4882a593Smuzhiyun};
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun&pmu_io_domains {
701*4882a593Smuzhiyun	pmu-supply = <&vcc_io>;
702*4882a593Smuzhiyun	vop-supply = <&vcc_io>;
703*4882a593Smuzhiyun	status = "okay";
704*4882a593Smuzhiyun};
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun&pwm0 {
707*4882a593Smuzhiyun	status = "okay";
708*4882a593Smuzhiyun};
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun&pwm1 {
711*4882a593Smuzhiyun	status = "okay";
712*4882a593Smuzhiyun};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun&uart0 {
715*4882a593Smuzhiyun	pinctrl-names = "default";
716*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
717*4882a593Smuzhiyun	status = "okay";
718*4882a593Smuzhiyun};
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun&u2phy {
721*4882a593Smuzhiyun	status = "okay";
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun	u2phy_host: host-port {
724*4882a593Smuzhiyun		phy-supply = <&vcc_host>;
725*4882a593Smuzhiyun		status = "okay";
726*4882a593Smuzhiyun	};
727*4882a593Smuzhiyun};
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun&usb_host0_ehci {
730*4882a593Smuzhiyun	status = "okay";
731*4882a593Smuzhiyun};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun&usb_host0_ohci {
734*4882a593Smuzhiyun	status = "okay";
735*4882a593Smuzhiyun};
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun&mailbox {
738*4882a593Smuzhiyun	status = "okay";
739*4882a593Smuzhiyun};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun&mailbox_scpi {
742*4882a593Smuzhiyun	status = "okay";
743*4882a593Smuzhiyun};
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun&saradc {
746*4882a593Smuzhiyun	status = "okay";
747*4882a593Smuzhiyun};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun&tsadc {
750*4882a593Smuzhiyun	tsadc-supply = <&syr827>;
751*4882a593Smuzhiyun	status = "okay";
752*4882a593Smuzhiyun};
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun&pinctrl {
755*4882a593Smuzhiyun	pmic {
756*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
757*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
758*4882a593Smuzhiyun		};
759*4882a593Smuzhiyun	};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun	usb2 {
762*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
763*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
764*4882a593Smuzhiyun		};
765*4882a593Smuzhiyun	};
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun	sdio-pwrseq {
768*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
769*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
770*4882a593Smuzhiyun		};
771*4882a593Smuzhiyun	};
772*4882a593Smuzhiyun};
773