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/OK3568_Linux_fs/kernel/arch/x86/include/asm/uv/
H A Duv_mmrs.h555 unsigned long lb_hcerr:1; /* RW */
561 unsigned long lb_hcerr:1; /* RW */
563 unsigned long rh_hcerr:1; /* RW */
564 unsigned long lh0_hcerr:1; /* RW */
565 unsigned long lh1_hcerr:1; /* RW */
566 unsigned long gr0_hcerr:1; /* RW */
567 unsigned long gr1_hcerr:1; /* RW */
568 unsigned long ni0_hcerr:1; /* RW */
569 unsigned long ni1_hcerr:1; /* RW */
570 unsigned long lb_aoerr0:1; /* RW */
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/OK3568_Linux_fs/yocto/poky/meta/lib/oeqa/files/
H A Dbuildhistory_filelist2.txt122 -rw-r--r-- root root 45 ./etc/bash_completion
124 -rw-r--r-- root root 447 ./etc/bindresvport.blacklist
125 -rw-r--r-- root root 521 ./etc/build
126 -rw-r--r-- root root 2370 ./etc/busybox.links.nosuid
127 -rw-r--r-- root root 91 ./etc/busybox.links.suid
129 -rw-r--r-- root root 5340 ./etc/ca-certificates.conf
132 -rw-r--r-- root root 838 ./etc/dbus-1/session.conf
133 -rw-r--r-- root root 833 ./etc/dbus-1/system.conf
136 -rw-r--r-- root root 36 ./etc/default/mountall
137 -rw-r--r-- root root 52 ./etc/default/postinst
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H A Dbuildhistory_filelist1.txt122 -rw-r--r-- root root 45 ./etc/bash_completion
124 -rw-r--r-- root root 447 ./etc/bindresvport.blacklist
125 -rw-r--r-- root root 506 ./etc/build
126 -rw-r--r-- root root 2370 ./etc/busybox.links.nosuid
127 -rw-r--r-- root root 91 ./etc/busybox.links.suid
129 -rw-r--r-- root root 5340 ./etc/ca-certificates.conf
132 -rw-r--r-- root root 838 ./etc/dbus-1/session.conf
133 -rw-r--r-- root root 833 ./etc/dbus-1/system.conf
136 -rw-r--r-- root root 36 ./etc/default/mountall
137 -rw-r--r-- root root 52 ./etc/default/postinst
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/OK3568_Linux_fs/kernel/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_rf2959.c32 static int bits(u32 rw, int from, int to)
34 rw &= ~(0xffffffffU << (to+1));
35 rw >>= from;
36 return rw;
39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
44 static void dump_regwrite(u32 rw)
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
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/OK3568_Linux_fs/external/rockit/mpi/sdk/include/
H A Drk_comm_venc.h203 RK_BOOL bSSEEn; /* RW; Range:[0,1]; Region SSE enable */
336 RK_BOOL bSupportDCF; /*RW; Range:[0,1]; support dcf */
337 VENC_MPF_CFG_S stMPFCfg; /*RW; Range:[0,1]; config of Mpf*/
371 RK_U32 u32StreamBufCnt; // RW; cache nums of encoded output
382 VENC_GOP_MODE_E enGopMode; /* RW; reference gop mode */
383 RK_S32 s32VirIdrLen; /* RW; virtual IDR frame length for smartp mode*/
384 …RK_U32 u32MaxLtrCount; /* RW; normalp and smartp mode switch without free Ltr buffer, setti…
397 RK_U32 u32BufLine; /* RW; Range: [128, H]; Chn buffer allocated by line. */
398 RK_U32 u32WrapBufferSize; /* RW; Whether to allocate buffer according to compression. */
409 RK_S32 s32ChnId; /* RW; Range: [0, VENC_MAX_CHN_NUM); The src combo channel */
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H A Drk_comm_rc.h60 RK_U32 u32Gop; // RW; Range:[1, 65536]; the interval of I Frame.
65 …RK_U32 u32BitRate; // RW; Range:[2, 200000]kbps; average bitrate; default : u32VirWidth*u32Vir…
66 RK_U32 u32StatTime; // RW; Range:[1,60]second;default : 3
71 RK_U32 u32Gop; // RW; Range:[1, 65536]; the interval of ISLICE.
76 …RK_U32 u32BitRate; // RW; Range:[2, 200000]kbps; average bitrate; default : u32VirWidth*u32Vir…
77 …RK_U32 u32MaxBitRate; // RW; Range:[u32BitRate, 200000]kbps; max bitrate; default : u32BitRate*3/…
78 RK_U32 u32MinBitRate; // RW; Range:[2, u32BitRate]kbps; min bitrate;; default : u32BitRate/2;
79 RK_U32 u32StatTime; // RW; Range:[1,60]second;default : 3
84 RK_U32 u32Gop; // RW; Range:[1, 65536]; the interval of ISLICE.
89 …RK_U32 u32BitRate; // RW; Range:[2, 200000]kbps; average bitrate; default : u32VirWidth*u32Vir…
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H A Drk_comm_gdc.h41 /* RW; Private data of task ; au64privateData[0]: stepx au64privateData[1]: stepy;
44 /* RW; Specify a task index, default 0 is not specify;[0,GDC_MAX_TASK_NUM);
70 FISHEYE_VIEW_MODE_E enViewMode; /* RW; Range: [0, 3];gdc view mode */
71 RK_U32 u32InRadius; /* RW; inner radius of gdc correction region*/
72 RK_U32 u32OutRadius; /* RW; out radius of gdc correction region*/
73 RK_U32 u32Pan; /* RW; Range: [0, 360] */
74 RK_U32 u32Tilt; /* RW; Range: [0, 360] */
75 RK_U32 u32HorZoom; /* RW; Range: [1, 4095] */
76 RK_U32 u32VerZoom; /* RW; Range: [1, 4095] */
77 RECT_S stOutRect; /* RW; out Imge rectangle attribute */
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H A Drk_comm_vo.h237 MIRROR_E enMirror; /* RW, Mirror */
238 ROTATION_E enRotation; /* RW, rotation. */
243 ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */
247 RK_BOOL bBorderEn; /* RW; Do frame or not */
248 BORDER_S stBorder; /* RW; frame's top, bottom, left, right width and color */
256 RK_BOOL bSynm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */
257 RK_BOOL bIop; /* RW; interlaced or progressive display(0:i; 1:p) */
259 RK_U16 u16Vact; /* RW; vertical active area */
260 RK_U16 u16Vbb; /* RW; vertical back blank porch */
261 RK_U16 u16Vfb; /* RW; vertical front blank porch */
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H A Drk_comm_vi.h102 /* RW;Interface mode */
104 /* RW;Work mode */
107 /* RW;Input data sequence (only the YUV format is supported) */
109 /* RW;RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable. */
111 /* RW;Input max size */
113 /* RW;Data rate of Device */
125 RK_U32 u32Num; /* RW;Range [1,VI_MAX_PHY_PIPE_NUM] */
126 VI_PIPE PipeId[MAX_VI_BIND_PIPE_NUM]; /* RW;Array of pipe ID */
131 /* RW;Range:[0,1];ISP bypass enable */
133 /* RW;Range:[0,1];Range[VI_PIPE_MIN_WIDTH,VI_PIPE_MAX_WIDTH];Maximum width */
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H A Drk_comm_vpss.h48 … RK_U32 u32MaxW; /* RW; Range: [64, 16384]; Width of source image. */
49 …RK_U32 u32MaxH; /* RW; Range: [64, 16384]; Height of source image. */
50 PIXEL_FORMAT_E enPixelFormat; /* RW; Pixel format of source image. */
51 DYNAMIC_RANGE_E enDynamicRange; /* RW; DynamicRange of source image. */
53 COMPRESS_MODE_E enCompressMode; /* RW; Reference frame compress mode */
54 RK_U32 u32MaxQueue; /* RW; Grp Max input queue length */
65 VPSS_CHN_MODE_E enChnMode; /* RW; Vpss channel's work mode. */
66 RK_U32 u32Width; /* RW; Range: [64, 16384]; Width of target image. */
67 RK_U32 u32Height; /* RW; Range: [64, 16384]; Height of target image. */
68 VIDEO_FORMAT_E enVideoFormat; /* RW; Video format of target image. */
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000e/
H A Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
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/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dkhadas-mcu.h36 #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
37 #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
38 #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
39 #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
40 #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
41 #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
42 #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
43 #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
44 #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
45 #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
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H A Dstmfx.h16 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
18 #define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */
19 #define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */
21 #define STMFX_REG_IRQ_ACK 0x44 /* RW */
29 #define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */
30 #define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */
31 #define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */
32 #define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */
33 #define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */
34 #define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igb/
H A De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
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/OK3568_Linux_fs/kernel/arch/ia64/include/asm/uv/
H A Duv_mmrs.h42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
49 unsigned long m : 1; /* RW */
51 unsigned long apic_id : 32; /* RW */
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
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/OK3568_Linux_fs/kernel/drivers/scsi/aic7xxx/
H A Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
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/OK3568_Linux_fs/kernel/arch/arc/include/asm/
H A Dspinlock.h79 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
87 * if (rw->counter > 0) { in arch_read_lock()
88 * rw->counter--; in arch_read_lock()
101 : [rwlock] "r" (&(rw->counter)), in arch_read_lock()
109 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
125 : [rwlock] "r" (&(rw->counter)), in arch_read_trylock()
134 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
144 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_lock()
145 * rw->counter = 0; in arch_write_lock()
158 : [rwlock] "r" (&(rw->counter)), in arch_write_lock()
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/OK3568_Linux_fs/external/rockit/mpi/example/mod/
H A Dtest_mpi_gdc.cpp494 …ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32InRadius = 0; /* RW; inner radius of gdc correct… in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
495 …ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32OutRadius = 474; /* RW; out radius of gdc correc… in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
496 ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32Pan = 180; /* RW; Range: [0, 360] */ in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
497 ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32Tilt = 98; /* RW; Range: [0, 360] */ in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
498 ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32HorZoom = 4095; /* RW; Range: [1, 4095] */ in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
499 ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32VerZoom = 4095; /* RW; Range: [1, 4095] */ in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
500 …ctx->stFisheyeAttr.astFishEyeRegionAttr[index].stOutRect.s32X = 0; /* RW; out Imge rectangle attri… in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
507 …ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32InRadius = 0; /* RW; inner radius of gdc correct… in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
508 …ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32OutRadius = 474; /* RW; out radius of gdc correc… in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
509 ctx->stFisheyeAttr.astFishEyeRegionAttr[index].u32Pan = 180; /* RW; Range: [0, 360] */ in test_mpi_gdc_desktop_ceil_mount_1p_add_1()
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/OK3568_Linux_fs/kernel/arch/parisc/include/asm/
H A Dspinlock.h67 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
73 arch_spin_lock(&(rw->lock_mutex)); in arch_read_trylock()
79 if (rw->counter > 0) { in arch_read_trylock()
80 rw->counter--; in arch_read_trylock()
84 arch_spin_unlock(&(rw->lock_mutex)); in arch_read_trylock()
91 static inline int arch_write_trylock(arch_rwlock_t *rw) in arch_write_trylock() argument
97 arch_spin_lock(&(rw->lock_mutex)); in arch_write_trylock()
105 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_trylock()
106 rw->counter = 0; in arch_write_trylock()
109 arch_spin_unlock(&(rw->lock_mutex)); in arch_write_trylock()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igc/
H A Digc_regs.h8 #define IGC_CTRL 0x00000 /* Device Control - RW */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_MDICNFG 0x00E04 /* MDC/MDIO Configuration - RW */
14 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
18 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
19 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
22 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
23 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
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/OK3568_Linux_fs/kernel/drivers/char/mwave/
H A D3780i.h68 unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
96 unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
97 unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
98 unsigned char Irq:3; /* RW: IRQ selection */
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/OK3568_Linux_fs/kernel/block/
H A Dblk-throttle.c299 static uint64_t tg_bps_limit(struct throtl_grp *tg, int rw) in tg_bps_limit() argument
309 ret = tg->bps[rw][td->limit_index]; in tg_bps_limit()
313 tg->iops[rw][td->limit_index]) in tg_bps_limit()
319 if (td->limit_index == LIMIT_MAX && tg->bps[rw][LIMIT_LOW] && in tg_bps_limit()
320 tg->bps[rw][LIMIT_LOW] != tg->bps[rw][LIMIT_MAX]) { in tg_bps_limit()
323 adjusted = throtl_adjusted_limit(tg->bps[rw][LIMIT_LOW], td); in tg_bps_limit()
324 ret = min(tg->bps[rw][LIMIT_MAX], adjusted); in tg_bps_limit()
329 static unsigned int tg_iops_limit(struct throtl_grp *tg, int rw) in tg_iops_limit() argument
339 ret = tg->iops[rw][td->limit_index]; in tg_iops_limit()
343 tg->bps[rw][td->limit_index]) in tg_iops_limit()
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