1*4882a593Smuzhiyun /* GPL-2.0 WITH Linux-syscall-note OR Apache 2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef INCLUDE_RT_MPI_RK_COMMON_VPSS_H_ 5*4882a593Smuzhiyun #define INCLUDE_RT_MPI_RK_COMMON_VPSS_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include "rk_type.h" 9*4882a593Smuzhiyun #include "rk_common.h" 10*4882a593Smuzhiyun #include "rk_errno.h" 11*4882a593Smuzhiyun #include "rk_comm_video.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef __cplusplus 14*4882a593Smuzhiyun #if __cplusplus 15*4882a593Smuzhiyun extern "C" { 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun #endif /* __cplusplus */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RK_VPSS_OK RK_SUCCESS 20*4882a593Smuzhiyun #define RK_ERR_VPSS_NULL_PTR RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NULL_PTR) 21*4882a593Smuzhiyun #define RK_ERR_VPSS_NOTREADY RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NOTREADY) 22*4882a593Smuzhiyun #define RK_ERR_VPSS_INVALID_DEVID RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_DEVID) 23*4882a593Smuzhiyun #define RK_ERR_VPSS_INVALID_CHNID RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_CHNID) 24*4882a593Smuzhiyun #define RK_ERR_VPSS_EXIST RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_EXIST) 25*4882a593Smuzhiyun #define RK_ERR_VPSS_UNEXIST RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_UNEXIST) 26*4882a593Smuzhiyun #define RK_ERR_VPSS_NOT_SUPPORT RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_SUPPORT) 27*4882a593Smuzhiyun #define RK_ERR_VPSS_NOT_PERM RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_PERM) 28*4882a593Smuzhiyun #define RK_ERR_VPSS_NOMEM RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NOMEM) 29*4882a593Smuzhiyun #define RK_ERR_VPSS_NOBUF RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_NOBUF) 30*4882a593Smuzhiyun #define RK_ERR_VPSS_SIZE_NOT_ENOUGH RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_SIZE_NOT_ENOUGH) 31*4882a593Smuzhiyun #define RK_ERR_VPSS_ILLEGAL_PARAM RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_ILLEGAL_PARAM) 32*4882a593Smuzhiyun #define RK_ERR_VPSS_BUSY RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_BUSY) 33*4882a593Smuzhiyun #define RK_ERR_VPSS_BUF_EMPTY RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_BUF_EMPTY) 34*4882a593Smuzhiyun #define RK_ERR_VPSS_BUF_FULL RK_DEF_ERR(RK_ID_VPSS, RK_ERR_LEVEL_ERROR, RK_ERR_BUF_FULL) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define VPSS_INVALID_FRMRATE -1 37*4882a593Smuzhiyun #define VPSS_CHN0 0 38*4882a593Smuzhiyun #define VPSS_CHN1 1 39*4882a593Smuzhiyun #define VPSS_CHN2 2 40*4882a593Smuzhiyun #define VPSS_CHN3 3 41*4882a593Smuzhiyun #define VPSS_INVALID_CHN -1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun typedef struct rkVPSS_MOD_PARAM_S { 44*4882a593Smuzhiyun MB_SOURCE_E enVpssMBSource; 45*4882a593Smuzhiyun } VPSS_MOD_PARAM_S; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun typedef struct rkVPSS_GRP_ATTR_S { 48*4882a593Smuzhiyun RK_U32 u32MaxW; /* RW; Range: [64, 16384]; Width of source image. */ 49*4882a593Smuzhiyun RK_U32 u32MaxH; /* RW; Range: [64, 16384]; Height of source image. */ 50*4882a593Smuzhiyun PIXEL_FORMAT_E enPixelFormat; /* RW; Pixel format of source image. */ 51*4882a593Smuzhiyun DYNAMIC_RANGE_E enDynamicRange; /* RW; DynamicRange of source image. */ 52*4882a593Smuzhiyun FRAME_RATE_CTRL_S stFrameRate; /* Grp frame rate contrl. */ 53*4882a593Smuzhiyun COMPRESS_MODE_E enCompressMode; /* RW; Reference frame compress mode */ 54*4882a593Smuzhiyun RK_U32 u32MaxQueue; /* RW; Grp Max input queue length */ 55*4882a593Smuzhiyun } VPSS_GRP_ATTR_S; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun typedef enum rkVPSS_CHN_MODE_E { 58*4882a593Smuzhiyun VPSS_CHN_MODE_USER = 0, /* User mode. */ 59*4882a593Smuzhiyun VPSS_CHN_MODE_AUTO = 1, /* Auto mode. */ 60*4882a593Smuzhiyun VPSS_CHN_MODE_PASSTHROUGH = 2, /* Pass through mode */ 61*4882a593Smuzhiyun VPSS_CHN_MODE_BUTT 62*4882a593Smuzhiyun } VPSS_CHN_MODE_E; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun typedef struct rkVPSS_CHN_ATTR_S { 65*4882a593Smuzhiyun VPSS_CHN_MODE_E enChnMode; /* RW; Vpss channel's work mode. */ 66*4882a593Smuzhiyun RK_U32 u32Width; /* RW; Range: [64, 16384]; Width of target image. */ 67*4882a593Smuzhiyun RK_U32 u32Height; /* RW; Range: [64, 16384]; Height of target image. */ 68*4882a593Smuzhiyun VIDEO_FORMAT_E enVideoFormat; /* RW; Video format of target image. */ 69*4882a593Smuzhiyun PIXEL_FORMAT_E enPixelFormat; /* RW; Pixel format of target image. */ 70*4882a593Smuzhiyun DYNAMIC_RANGE_E enDynamicRange; /* RW; DynamicRange of target image. */ 71*4882a593Smuzhiyun COMPRESS_MODE_E enCompressMode; /* RW; Compression mode of the output. */ 72*4882a593Smuzhiyun FRAME_RATE_CTRL_S stFrameRate; /* Frame rate control info */ 73*4882a593Smuzhiyun RK_BOOL bMirror; /* RW; Mirror enable. */ 74*4882a593Smuzhiyun RK_BOOL bFlip; /* RW; Flip enable. */ 75*4882a593Smuzhiyun RK_U32 u32Depth; /* RW; Range: [0, 8]; User get list depth. */ 76*4882a593Smuzhiyun ASPECT_RATIO_S stAspectRatio; /* Aspect Ratio info. */ 77*4882a593Smuzhiyun RK_U32 u32FrameBufCnt; /* RW; frame buffer cnt only used by MB_SOURCE_PRIVATE */ 78*4882a593Smuzhiyun } VPSS_CHN_ATTR_S; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun typedef enum rkVPSS_CROP_COORDINATE_E { 81*4882a593Smuzhiyun VPSS_CROP_RATIO_COOR = 0, /* Ratio coordinate. */ 82*4882a593Smuzhiyun VPSS_CROP_ABS_COOR /* Absolute coordinate. */ 83*4882a593Smuzhiyun } VPSS_CROP_COORDINATE_E; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun typedef struct rkVPSS_CROP_INFO_S { 86*4882a593Smuzhiyun RK_BOOL bEnable; /* RW; Range: [0, 1]; CROP enable. */ 87*4882a593Smuzhiyun VPSS_CROP_COORDINATE_E enCropCoordinate; /* RW; Range: [0, 1]; Coordinate mode of the crop start point. */ 88*4882a593Smuzhiyun RECT_S stCropRect; /* CROP rectangular. */ 89*4882a593Smuzhiyun } VPSS_CROP_INFO_S; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun typedef struct rkVPSS_ROTATION_EX_ATTR_S { 92*4882a593Smuzhiyun RK_BOOL bEnable; /* Whether ROTATE_EX_S is enbale */ 93*4882a593Smuzhiyun ROTATION_EX_S stRotationEx; /* Rotate Attribute */ 94*4882a593Smuzhiyun } VPSS_ROTATION_EX_ATTR_S; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #ifdef __cplusplus 97*4882a593Smuzhiyun #if __cplusplus 98*4882a593Smuzhiyun } 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun #endif /* __cplusplus */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* INCLUDE_RT_MPI_RK_COMMON_VPSS_H_ */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 105