1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013,2014 ARM Limited 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 5*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 6*4882a593Smuzhiyun * for more details. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * ARM HDLCD Controller register definition 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __HDLCD_REGS_H__ 12*4882a593Smuzhiyun #define __HDLCD_REGS_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* register offsets */ 15*4882a593Smuzhiyun #define HDLCD_REG_VERSION 0x0000 /* ro */ 16*4882a593Smuzhiyun #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */ 17*4882a593Smuzhiyun #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */ 18*4882a593Smuzhiyun #define HDLCD_REG_INT_MASK 0x0018 /* rw */ 19*4882a593Smuzhiyun #define HDLCD_REG_INT_STATUS 0x001c /* ro */ 20*4882a593Smuzhiyun #define HDLCD_REG_FB_BASE 0x0100 /* rw */ 21*4882a593Smuzhiyun #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */ 22*4882a593Smuzhiyun #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */ 23*4882a593Smuzhiyun #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */ 24*4882a593Smuzhiyun #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */ 25*4882a593Smuzhiyun #define HDLCD_REG_V_SYNC 0x0200 /* rw */ 26*4882a593Smuzhiyun #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */ 27*4882a593Smuzhiyun #define HDLCD_REG_V_DATA 0x0208 /* rw */ 28*4882a593Smuzhiyun #define HDLCD_REG_V_FRONT_PORCH 0x020c /* rw */ 29*4882a593Smuzhiyun #define HDLCD_REG_H_SYNC 0x0210 /* rw */ 30*4882a593Smuzhiyun #define HDLCD_REG_H_BACK_PORCH 0x0214 /* rw */ 31*4882a593Smuzhiyun #define HDLCD_REG_H_DATA 0x0218 /* rw */ 32*4882a593Smuzhiyun #define HDLCD_REG_H_FRONT_PORCH 0x021c /* rw */ 33*4882a593Smuzhiyun #define HDLCD_REG_POLARITIES 0x0220 /* rw */ 34*4882a593Smuzhiyun #define HDLCD_REG_COMMAND 0x0230 /* rw */ 35*4882a593Smuzhiyun #define HDLCD_REG_PIXEL_FORMAT 0x0240 /* rw */ 36*4882a593Smuzhiyun #define HDLCD_REG_RED_SELECT 0x0244 /* rw */ 37*4882a593Smuzhiyun #define HDLCD_REG_GREEN_SELECT 0x0248 /* rw */ 38*4882a593Smuzhiyun #define HDLCD_REG_BLUE_SELECT 0x024c /* rw */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* version */ 41*4882a593Smuzhiyun #define HDLCD_PRODUCT_ID 0x1CDC0000 42*4882a593Smuzhiyun #define HDLCD_PRODUCT_MASK 0xFFFF0000 43*4882a593Smuzhiyun #define HDLCD_VERSION_MAJOR_MASK 0x0000FF00 44*4882a593Smuzhiyun #define HDLCD_VERSION_MINOR_MASK 0x000000FF 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* interrupts */ 47*4882a593Smuzhiyun #define HDLCD_INTERRUPT_DMA_END (1 << 0) 48*4882a593Smuzhiyun #define HDLCD_INTERRUPT_BUS_ERROR (1 << 1) 49*4882a593Smuzhiyun #define HDLCD_INTERRUPT_VSYNC (1 << 2) 50*4882a593Smuzhiyun #define HDLCD_INTERRUPT_UNDERRUN (1 << 3) 51*4882a593Smuzhiyun #define HDLCD_DEBUG_INT_MASK (HDLCD_INTERRUPT_DMA_END | \ 52*4882a593Smuzhiyun HDLCD_INTERRUPT_BUS_ERROR | \ 53*4882a593Smuzhiyun HDLCD_INTERRUPT_UNDERRUN) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* polarities */ 56*4882a593Smuzhiyun #define HDLCD_POLARITY_VSYNC (1 << 0) 57*4882a593Smuzhiyun #define HDLCD_POLARITY_HSYNC (1 << 1) 58*4882a593Smuzhiyun #define HDLCD_POLARITY_DATAEN (1 << 2) 59*4882a593Smuzhiyun #define HDLCD_POLARITY_DATA (1 << 3) 60*4882a593Smuzhiyun #define HDLCD_POLARITY_PIXELCLK (1 << 4) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* commands */ 63*4882a593Smuzhiyun #define HDLCD_COMMAND_DISABLE (0 << 0) 64*4882a593Smuzhiyun #define HDLCD_COMMAND_ENABLE (1 << 0) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* pixel format */ 67*4882a593Smuzhiyun #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN (0 << 31) 68*4882a593Smuzhiyun #define HDLCD_PIXEL_FMT_BIG_ENDIAN (1 << 31) 69*4882a593Smuzhiyun #define HDLCD_BYTES_PER_PIXEL_MASK (3 << 3) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* bus options */ 72*4882a593Smuzhiyun #define HDLCD_BUS_BURST_MASK 0x01f 73*4882a593Smuzhiyun #define HDLCD_BUS_MAX_OUTSTAND 0xf00 74*4882a593Smuzhiyun #define HDLCD_BUS_BURST_NONE (0 << 0) 75*4882a593Smuzhiyun #define HDLCD_BUS_BURST_1 (1 << 0) 76*4882a593Smuzhiyun #define HDLCD_BUS_BURST_2 (1 << 1) 77*4882a593Smuzhiyun #define HDLCD_BUS_BURST_4 (1 << 2) 78*4882a593Smuzhiyun #define HDLCD_BUS_BURST_8 (1 << 3) 79*4882a593Smuzhiyun #define HDLCD_BUS_BURST_16 (1 << 4) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Max resolution supported is 4096x4096, 32bpp */ 82*4882a593Smuzhiyun #define HDLCD_MAX_XRES 4096 83*4882a593Smuzhiyun #define HDLCD_MAX_YRES 4096 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define NR_PALETTE 256 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* __HDLCD_REGS_H__ */ 88