xref: /OK3568_Linux_fs/external/rockit/mpi/sdk/include/rk_comm_vo.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* GPL-2.0 WITH Linux-syscall-note OR Apache 2.0 */
2*4882a593Smuzhiyun /* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #ifndef INCLUDE_RT_MPI_RK_COMMON_VO_H_
5*4882a593Smuzhiyun #define INCLUDE_RT_MPI_RK_COMMON_VO_H_
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include "rk_type.h"
8*4882a593Smuzhiyun #include "rk_common.h"
9*4882a593Smuzhiyun #include "rk_comm_video.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define VO_DEF_WBC_DEPTH_LEN    8
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #ifdef __cplusplus
14*4882a593Smuzhiyun #if __cplusplus
15*4882a593Smuzhiyun extern "C" {
16*4882a593Smuzhiyun #endif
17*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun typedef enum rkEN_VOU_ERR_CODE_E {
20*4882a593Smuzhiyun     EN_ERR_VO_DEV_NOT_CONFIG = 0x40,
21*4882a593Smuzhiyun     EN_ERR_VO_DEV_NOT_ENABLE = 0x41,
22*4882a593Smuzhiyun     EN_ERR_VO_DEV_HAS_ENABLED = 0x42,
23*4882a593Smuzhiyun     EN_ERR_VO_DEV_HAS_BINDED = 0x43,
24*4882a593Smuzhiyun     EN_ERR_VO_DEV_NOT_BINDED = 0x44,
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun     ERR_VO_NOT_ENABLE = 0x45,
27*4882a593Smuzhiyun     ERR_VO_NOT_DISABLE = 0x46,
28*4882a593Smuzhiyun     ERR_VO_NOT_CONFIG = 0x47,
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun     ERR_VO_CHN_NOT_DISABLE = 0x48,
31*4882a593Smuzhiyun     ERR_VO_CHN_NOT_ENABLE = 0x49,
32*4882a593Smuzhiyun     ERR_VO_CHN_NOT_CONFIG = 0x4a,
33*4882a593Smuzhiyun     ERR_VO_CHN_NOT_ALLOC = 0x4b,
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun     ERR_VO_CCD_INVALID_PAT = 0x4c,
36*4882a593Smuzhiyun     ERR_VO_CCD_INVALID_POS = 0x4d,
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun     ERR_VO_WAIT_TIMEOUT = 0x4e,
39*4882a593Smuzhiyun     ERR_VO_INVALID_VFRAME = 0x4f,
40*4882a593Smuzhiyun     ERR_VO_INVALID_RECT_PARA = 0x50,
41*4882a593Smuzhiyun     ERR_VO_SETBEGIN_ALREADY = 0x51,
42*4882a593Smuzhiyun     ERR_VO_SETBEGIN_NOTYET = 0x52,
43*4882a593Smuzhiyun     ERR_VO_SETEND_ALREADY = 0x53,
44*4882a593Smuzhiyun     ERR_VO_SETEND_NOTYET = 0x54,
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun     ERR_VO_WBC_NOT_DISABLE = 0x55,
47*4882a593Smuzhiyun     ERR_VO_WBC_NOT_CONFIG = 0x56,
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun     ERR_VO_CHN_AREA_OVERLAP = 0x57,
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun     EN_ERR_INVALID_WBCID = 0x58,
52*4882a593Smuzhiyun     EN_ERR_INVALID_LAYERID = 0x59,
53*4882a593Smuzhiyun     EN_ERR_VO_LAYER_HAS_BINDED = 0x5a,
54*4882a593Smuzhiyun     EN_ERR_VO_LAYER_NOT_BINDED = 0x5b,
55*4882a593Smuzhiyun     ERR_VO_WBC_HAS_BIND = 0x5c,
56*4882a593Smuzhiyun     ERR_VO_WBC_HAS_CONFIG = 0x5d,
57*4882a593Smuzhiyun     ERR_VO_WBC_NOT_BIND = 0x5e,
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun     /* new added */
60*4882a593Smuzhiyun     ERR_VO_BUTT
61*4882a593Smuzhiyun } EN_VOU_ERR_CODE_E;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* System define error code */
64*4882a593Smuzhiyun #define RK_ERR_VO_BUSY                 RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_BUSY)
65*4882a593Smuzhiyun #define RK_ERR_VO_NO_MEM               RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOMEM)
66*4882a593Smuzhiyun #define RK_ERR_VO_NULL_PTR             RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NULL_PTR)
67*4882a593Smuzhiyun #define RK_ERR_VO_SYS_NOTREADY         RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOTREADY)
68*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_DEVID        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_DEVID)
69*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_CHNID        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_CHNID)
70*4882a593Smuzhiyun #define RK_ERR_VO_ILLEGAL_PARAM        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_ILLEGAL_PARAM)
71*4882a593Smuzhiyun #define RK_ERR_VO_NOT_SUPPORT          RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_SUPPORT)
72*4882a593Smuzhiyun #define RK_ERR_VO_NOT_PERMIT           RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_PERM)
73*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_WBCID        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_INVALID_WBCID)
74*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_LAYERID      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_INVALID_LAYERID)
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Device relative error code */
77*4882a593Smuzhiyun #define RK_ERR_VO_DEV_NOT_CONFIG       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG)
78*4882a593Smuzhiyun #define RK_ERR_VO_DEV_NOT_ENABLE       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLE)
79*4882a593Smuzhiyun #define RK_ERR_VO_DEV_HAS_ENABLED      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED)
80*4882a593Smuzhiyun #define RK_ERR_VO_DEV_HAS_BINDED       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_BINDED)
81*4882a593Smuzhiyun #define RK_ERR_VO_DEV_NOT_BINDED       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_BINDED)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* layer relative error code */
84*4882a593Smuzhiyun #define RK_ERR_VO_LAYER_NOT_ENABLE     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_ENABLE)
85*4882a593Smuzhiyun #define RK_ERR_VO_LAYER_NOT_DISABLE    RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_DISABLE)
86*4882a593Smuzhiyun #define RK_ERR_VO_LAYER_NOT_CONFIG     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_CONFIG)
87*4882a593Smuzhiyun #define RK_ERR_VO_LAYER_HAS_BINDED     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_HAS_BINDED)
88*4882a593Smuzhiyun #define RK_ERR_VO_LAYER_NOT_BINDED     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_NOT_BINDED)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* WBC Relative error code */
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define RK_ERR_VO_WBC_NOT_DISABLE      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_DISABLE)
93*4882a593Smuzhiyun #define RK_ERR_VO_WBC_NOT_CONFIG       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_CONFIG)
94*4882a593Smuzhiyun #define RK_ERR_VO_WBC_HAS_CONFIG       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_CONFIG)
95*4882a593Smuzhiyun #define RK_ERR_VO_WBC_NOT_BIND         RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_BIND)
96*4882a593Smuzhiyun #define RK_ERR_VO_WBC_HAS_BIND         RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_BIND)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* Channel Relative error code */
99*4882a593Smuzhiyun #define RK_ERR_VO_CHN_NOT_DISABLE      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_DISABLE)
100*4882a593Smuzhiyun #define RK_ERR_VO_CHN_NOT_ENABLE       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ENABLE)
101*4882a593Smuzhiyun #define RK_ERR_VO_CHN_NOT_CONFIG       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_CONFIG)
102*4882a593Smuzhiyun #define RK_ERR_VO_CHN_NOT_ALLOC        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ALLOC)
103*4882a593Smuzhiyun #define RK_ERR_VO_CHN_AREA_OVERLAP     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_AREA_OVERLAP)
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* Cascade Relatvie error code */
106*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_PATTERN      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_PAT)
107*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_POSITION     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_POS)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* MISCellaneous error code */
110*4882a593Smuzhiyun #define RK_ERR_VO_WAIT_TIMEOUT         RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WAIT_TIMEOUT)
111*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_VFRAME       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_INVALID_VFRAME)
112*4882a593Smuzhiyun #define RK_ERR_VO_INVALID_RECT_PARA    RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_INVALID_RECT_PARA)
113*4882a593Smuzhiyun #define RK_ERR_VO_SETBEGIN_ALREADY     RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_ALREADY)
114*4882a593Smuzhiyun #define RK_ERR_VO_SETBEGIN_NOTYET      RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_NOTYET)
115*4882a593Smuzhiyun #define RK_ERR_VO_SETEND_ALREADY       RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETEND_ALREADY)
116*4882a593Smuzhiyun #define RK_ERR_VO_SETEND_NOTYET        RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETEND_NOTYET)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* VO video output interface type */
119*4882a593Smuzhiyun #define VO_INTF_CVBS                   (0x01L << 0)
120*4882a593Smuzhiyun #define VO_INTF_YPBPR                  (0x01L << 1)
121*4882a593Smuzhiyun #define VO_INTF_VGA                    (0x01L << 2)
122*4882a593Smuzhiyun #define VO_INTF_BT656                  (0x01L << 3)
123*4882a593Smuzhiyun #define VO_INTF_BT1120                 (0x01L << 4)
124*4882a593Smuzhiyun #define VO_INTF_LCD                    (0x01L << 6)
125*4882a593Smuzhiyun #define VO_INTF_LVDS                   (0x01L << 7)
126*4882a593Smuzhiyun #define VO_INTF_MIPI                   (0x01L << 9)
127*4882a593Smuzhiyun #define VO_INTF_MIPI1                  (0x01L << 10)
128*4882a593Smuzhiyun #define VO_INTF_EDP                    (0x01L << 11)
129*4882a593Smuzhiyun #define VO_INTF_EDP1                   (0x01L << 12)
130*4882a593Smuzhiyun #define VO_INTF_HDMI                   (0x01L << 13)
131*4882a593Smuzhiyun #define VO_INTF_HDMI1                  (0x01L << 14)
132*4882a593Smuzhiyun #define VO_INTF_DP                     (0x01L << 15)
133*4882a593Smuzhiyun #define VO_INTF_DP1                    (0x01L << 16)
134*4882a593Smuzhiyun #define VO_INTF_DEFAULT                (0x01L << 17)
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define VO_INTF_NUM                     17
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun typedef RK_U32 VO_INTF_TYPE_E;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun typedef enum rkVO_INTF_SYNC_E {
141*4882a593Smuzhiyun     VO_OUTPUT_PAL = 0, /* PAL standard */
142*4882a593Smuzhiyun     VO_OUTPUT_NTSC, /* NTSC standard */
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun     VO_OUTPUT_1080P24, /* 1920 x 1080 at 24 Hz. */
145*4882a593Smuzhiyun     VO_OUTPUT_1080P25, /* 1920 x 1080 at 25 Hz. */
146*4882a593Smuzhiyun     VO_OUTPUT_1080P30, /* 1920 x 1080 at 30 Hz. */
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun     VO_OUTPUT_720P50, /* 1280 x  720 at 50 Hz. */
149*4882a593Smuzhiyun     VO_OUTPUT_720P60, /* 1280 x  720 at 60 Hz. */
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun     VO_OUTPUT_1080I50, /* 1920 x 1080 at 50 Hz, interlace. */
152*4882a593Smuzhiyun     VO_OUTPUT_1080I60, /* 1920 x 1080 at 60 Hz, interlace. */
153*4882a593Smuzhiyun     VO_OUTPUT_1080P50, /* 1920 x 1080 at 50 Hz. */
154*4882a593Smuzhiyun     VO_OUTPUT_1080P60, /* 1920 x 1080 at 60 Hz. */
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun     VO_OUTPUT_576P50, /* 720  x  576 at 50 Hz. */
157*4882a593Smuzhiyun     VO_OUTPUT_480P60, /* 720  x  480 at 60 Hz. */
158*4882a593Smuzhiyun     VO_OUTPUT_1280P60, /* 720  x  1280 at 60 Hz. */
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun     VO_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */
161*4882a593Smuzhiyun     VO_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
162*4882a593Smuzhiyun     VO_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
163*4882a593Smuzhiyun     VO_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
164*4882a593Smuzhiyun     VO_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
165*4882a593Smuzhiyun     VO_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz */
166*4882a593Smuzhiyun     VO_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
167*4882a593Smuzhiyun     VO_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
168*4882a593Smuzhiyun     VO_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */
169*4882a593Smuzhiyun     VO_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
170*4882a593Smuzhiyun     VO_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */
171*4882a593Smuzhiyun     VO_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */
172*4882a593Smuzhiyun     VO_OUTPUT_1920x2160_30, /* 1920x2160_30 */
173*4882a593Smuzhiyun     VO_OUTPUT_2560x1440_30, /* 2560x1440_30 */
174*4882a593Smuzhiyun     VO_OUTPUT_2560x1440_60, /* 2560x1440_60 */
175*4882a593Smuzhiyun     VO_OUTPUT_2560x1600_60, /* 2560x1600_60 */
176*4882a593Smuzhiyun     VO_OUTPUT_3840x2160_24, /* 3840x2160_24 */
177*4882a593Smuzhiyun     VO_OUTPUT_3840x2160_25, /* 3840x2160_25 */
178*4882a593Smuzhiyun     VO_OUTPUT_3840x2160_30, /* 3840x2160_30 */
179*4882a593Smuzhiyun     VO_OUTPUT_3840x2160_50, /* 3840x2160_50 */
180*4882a593Smuzhiyun     VO_OUTPUT_3840x2160_60, /* 3840x2160_60 */
181*4882a593Smuzhiyun     VO_OUTPUT_4096x2160_24, /* 4096x2160_24 */
182*4882a593Smuzhiyun     VO_OUTPUT_4096x2160_25, /* 4096x2160_25 */
183*4882a593Smuzhiyun     VO_OUTPUT_4096x2160_30, /* 4096x2160_30 */
184*4882a593Smuzhiyun     VO_OUTPUT_4096x2160_50, /* 4096x2160_50 */
185*4882a593Smuzhiyun     VO_OUTPUT_4096x2160_60, /* 4096x2160_60 */
186*4882a593Smuzhiyun     /* For HDMI2.1  */
187*4882a593Smuzhiyun     VO_OUTPUT_7680x4320_24, /* 7680x4320_24 */
188*4882a593Smuzhiyun     VO_OUTPUT_7680x4320_25, /* 7680x4320_25 */
189*4882a593Smuzhiyun     VO_OUTPUT_7680x4320_30, /* 7680x4320_30 */
190*4882a593Smuzhiyun     VO_OUTPUT_7680x4320_50, /* 7680x4320_50 */
191*4882a593Smuzhiyun     VO_OUTPUT_7680x4320_60, /* 7680x4320_60 */
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun     VO_OUTPUT_3840x1080_60, /* For split mode */
194*4882a593Smuzhiyun     VO_OUTPUT_1080P120, /* 1920x1080_120 */
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun     VO_OUTPUT_USER, /* User timing. */
197*4882a593Smuzhiyun     VO_OUTPUT_DEFAULT,
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun     VO_OUTPUT_BUTT
200*4882a593Smuzhiyun } VO_INTF_SYNC_E;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun typedef enum rkVO_ZOOM_IN_E {
203*4882a593Smuzhiyun     VO_ZOOM_IN_RECT = 0, /* Zoom in by rect */
204*4882a593Smuzhiyun     VO_ZOOM_IN_RATIO, /* Zoom in by ratio */
205*4882a593Smuzhiyun     VO_ZOOM_IN_BUTT
206*4882a593Smuzhiyun } VO_ZOOM_IN_E;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun typedef enum rkVO_CSC_MATRIX_E {
209*4882a593Smuzhiyun     VO_CSC_MATRIX_IDENTITY = 0, /* Identity CSC matrix. */
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun     VO_CSC_MATRIX_BT601_TO_BT709, /* BT601 to BT709 */
212*4882a593Smuzhiyun     VO_CSC_MATRIX_BT709_TO_BT601, /* BT709 to BT601 */
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun     VO_CSC_MATRIX_BT601_TO_RGB_PC, /* BT601 to RGB */
215*4882a593Smuzhiyun     VO_CSC_MATRIX_BT709_TO_RGB_PC, /* BT709 to RGB */
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun     VO_CSC_MATRIX_RGB_TO_BT601_PC, /* RGB to BT601 FULL */
218*4882a593Smuzhiyun     VO_CSC_MATRIX_RGB_TO_BT709_PC, /* RGB to BT709 FULL */
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun     VO_CSC_MATRIX_RGB_TO_BT2020_PC, /* RGB to BT.2020 */
221*4882a593Smuzhiyun     VO_CSC_MATRIX_BT2020_TO_RGB_PC, /* BT.2020 to RGB */
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun     VO_CSC_MATRIX_RGB_TO_BT601_TV, /* RGB to BT601 LIMIT */
224*4882a593Smuzhiyun     VO_CSC_MATRIX_RGB_TO_BT709_TV, /* RGB to BT709 LIMIT */
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun     VO_CSC_MATRIX_BUTT
227*4882a593Smuzhiyun } VO_CSC_MATRIX_E;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun typedef struct rkVO_CHN_ATTR_S {
230*4882a593Smuzhiyun     RK_U32 u32Priority; /* Video out overlay pri sd */
231*4882a593Smuzhiyun     RECT_S stRect;      /* Rectangle of video output channel */
232*4882a593Smuzhiyun     RK_BOOL bDeflicker; /* Deflicker or not sd */
233*4882a593Smuzhiyun     RK_U32 u32FgAlpha;  /* Alpha of A = 1 in pixel format BGRA5551/RGBA5551 */
234*4882a593Smuzhiyun     RK_U32 u32BgAlpha;  /* Alpha of A = 0 in pixel format BGRA5551/RGBA5551 */
235*4882a593Smuzhiyun     RK_BOOL bEnKeyColor;/* Enable key color or not when pixel format BGRA5551/RGBA5551 */
236*4882a593Smuzhiyun     RK_U32 u32KeyColor; /* Key color value of pixel format BGRA5551/RGBA5551, B[0:4] G[5:9] R[10:14] */
237*4882a593Smuzhiyun     MIRROR_E enMirror; /* RW, Mirror */
238*4882a593Smuzhiyun     ROTATION_E enRotation;    /* RW, rotation. */
239*4882a593Smuzhiyun     RK_U32 u32MaxChnQueue;    /* vo channel max queue length */
240*4882a593Smuzhiyun } VO_CHN_ATTR_S;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun typedef struct rkVO_CHN_PARAM_S {
243*4882a593Smuzhiyun     ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */
244*4882a593Smuzhiyun } VO_CHN_PARAM_S;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun typedef struct rkVO_BORDER_S {
247*4882a593Smuzhiyun     RK_BOOL bBorderEn; /* RW; Do frame or not */
248*4882a593Smuzhiyun     BORDER_S stBorder; /* RW; frame's top, bottom, left, right width and color */
249*4882a593Smuzhiyun } VO_BORDER_S;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun typedef struct rkVO_QUERY_STATUS_S {
252*4882a593Smuzhiyun     RK_U32 u32ChnBufUsed; /* Channel buffer that been occupied */
253*4882a593Smuzhiyun } VO_QUERY_STATUS_S;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun typedef struct rkVO_SYNC_INFO_S {
256*4882a593Smuzhiyun     RK_BOOL bSynm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */
257*4882a593Smuzhiyun     RK_BOOL bIop; /* RW; interlaced or progressive display(0:i; 1:p) */
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun     RK_U16 u16Vact; /* RW; vertical active area */
260*4882a593Smuzhiyun     RK_U16 u16Vbb; /* RW; vertical back blank porch */
261*4882a593Smuzhiyun     RK_U16 u16Vfb; /* RW; vertical front blank porch */
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun     RK_U16 u16Hact; /* RW; horizontal active area */
264*4882a593Smuzhiyun     RK_U16 u16Hbb; /* RW; horizontal back blank porch */
265*4882a593Smuzhiyun     RK_U16 u16Hfb; /* RW; horizontal front blank porch */
266*4882a593Smuzhiyun     RK_U16 u16Hmid; /* RW; bottom horizontal active area */
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun     RK_U16 u16Bvact; /* RW; bottom vertical active area */
269*4882a593Smuzhiyun     RK_U16 u16Bvbb; /* RW; bottom vertical back blank porch */
270*4882a593Smuzhiyun     RK_U16 u16Bvfb; /* RW; bottom vertical front blank porch */
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun     RK_U16 u16Hpw; /* RW; horizontal pulse width */
273*4882a593Smuzhiyun     RK_U16 u16Vpw; /* RW; vertical pulse width */
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun     RK_BOOL bIdv; /* RW; inverse data valid of output */
276*4882a593Smuzhiyun     RK_BOOL bIhs; /* RW; polarity of horizontal synch signal, 0: negative, 1: positive */
277*4882a593Smuzhiyun     RK_BOOL bIvs; /* RW; polarity of vertical synch signal, 0: negative, 1: positive */
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun     RK_U16 u16FrameRate; /* RW; frame rate of output */
280*4882a593Smuzhiyun     RK_U32 u32PixClock; /* RW; pixel clock, the unit is KHZ */
281*4882a593Smuzhiyun } VO_SYNC_INFO_S;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun typedef struct rkVO_PUB_ATTR_S {
284*4882a593Smuzhiyun     RK_U32 u32BgColor;          /* RW; Background color of a device, in RGB format. */
285*4882a593Smuzhiyun     VO_INTF_TYPE_E enIntfType;  /* RW; Type of a VO interface */
286*4882a593Smuzhiyun     VO_INTF_SYNC_E enIntfSync;  /* RW; Type of a VO interface timing */
287*4882a593Smuzhiyun     VO_SYNC_INFO_S stSyncInfo;  /* RW; Information about VO interface timings */
288*4882a593Smuzhiyun } VO_PUB_ATTR_S;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun typedef struct rkVO_WBC_ATTR_S {
291*4882a593Smuzhiyun     SIZE_S stTargetSize; /* RW; WBC Zoom target size */
292*4882a593Smuzhiyun     PIXEL_FORMAT_E enPixelFormat; /* RW; the pixel format of WBC output */
293*4882a593Smuzhiyun     RK_U32 u32FrameRate; /* RW; frame rate control */
294*4882a593Smuzhiyun     DYNAMIC_RANGE_E enDynamicRange; /* RW; Write back dynamic range type */
295*4882a593Smuzhiyun     COMPRESS_MODE_E enCompressMode; /* RW; Write back Compressing mode   */
296*4882a593Smuzhiyun } VO_WBC_ATTR_S;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun typedef enum rkVO_WBC_MODE_E {
299*4882a593Smuzhiyun     /*
300*4882a593Smuzhiyun      * In this mode, wbc will capture frames according
301*4882a593Smuzhiyun      * to dev frame rate and wbc frame rate
302*4882a593Smuzhiyun      */
303*4882a593Smuzhiyun     VO_WBC_MODE_NORMAL = 0,
304*4882a593Smuzhiyun     /*
305*4882a593Smuzhiyun      * In this mode, wbc will drop dev repeat frame,
306*4882a593Smuzhiyun      * and capture the real frame according to video layer's
307*4882a593Smuzhiyun      * display rate and wbc frame rate
308*4882a593Smuzhiyun      */
309*4882a593Smuzhiyun     VO_WBC_MODE_DROP_REPEAT,
310*4882a593Smuzhiyun      /*
311*4882a593Smuzhiyun       * In this mode, wbc will drop dev repeat frame
312*4882a593Smuzhiyun       * which repeats more than 3 times, and change
313*4882a593Smuzhiyun       * two progressive frames to one interlace frame
314*4882a593Smuzhiyun       */
315*4882a593Smuzhiyun     VO_WBC_MODE_PROG_TO_INTL,
316*4882a593Smuzhiyun     VO_WBC_MODE_BUTT,
317*4882a593Smuzhiyun } VO_WBC_MODE_E;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun typedef enum rkVO_WBC_SOURCE_TYPE_E {
320*4882a593Smuzhiyun     VO_WBC_SOURCE_DEV = 0x0, /* WBC source is device */
321*4882a593Smuzhiyun     VO_WBC_SOURCE_VIDEO = 0x1, /* WBC source is video layer */
322*4882a593Smuzhiyun     VO_WBC_SOURCE_GRAPHIC = 0x2, /* WBC source is graphic layer. Warning: not supported */
323*4882a593Smuzhiyun     VO_WBC_SOURCE_VIRTUAL = 0x3, /* WBC source is virtual layer */
324*4882a593Smuzhiyun     VO_WBC_SOURCE_BUTT
325*4882a593Smuzhiyun } VO_WBC_SOURCE_TYPE_E;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun typedef struct rkVO_WBC_SOURCE_S {
328*4882a593Smuzhiyun     VO_WBC_SOURCE_TYPE_E enSourceType; /* RW; WBC source's type */
329*4882a593Smuzhiyun     RK_U32 u32SourceId; /* RW; WBC source's ID */
330*4882a593Smuzhiyun } VO_WBC_SOURCE_S;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun typedef enum rkVO_PART_MODE_E {
333*4882a593Smuzhiyun     VO_PART_MODE_SINGLE = 0, /* single partition, which use software to make multi-picture in one hardware cell */
334*4882a593Smuzhiyun     VO_PART_MODE_MULTI = 1, /* muliti partition, each partition is a hardware cell */
335*4882a593Smuzhiyun     VO_PART_MODE_BUTT
336*4882a593Smuzhiyun } VO_PART_MODE_E;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun typedef enum rkVO_SPLICE_MODE_E {
339*4882a593Smuzhiyun     VO_SPLICE_MODE_GPU = 0,
340*4882a593Smuzhiyun     VO_SPLICE_MODE_RGA
341*4882a593Smuzhiyun } VO_SPLICE_MODE_E;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun typedef enum rkVO_LAYER_MODE_E {
344*4882a593Smuzhiyun     VO_LAYER_MODE_CURSOR = 0,
345*4882a593Smuzhiyun     VO_LAYER_MODE_GRAPHIC,
346*4882a593Smuzhiyun     VO_LAYER_MODE_VIDEO,
347*4882a593Smuzhiyun     VO_LAYER_MODE_VIRTUAL,
348*4882a593Smuzhiyun     VO_LAYER_MODE_BUTT
349*4882a593Smuzhiyun } VO_LAYER_MODE_E;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun typedef struct rkVO_VIDEO_LAYER_ATTR_S {
352*4882a593Smuzhiyun     RECT_S stDispRect; /* RW; Display resolution */
353*4882a593Smuzhiyun     SIZE_S stImageSize; /* RW; Canvas size of the video layer */
354*4882a593Smuzhiyun     RK_U32 u32DispFrmRt; /* RW; Display frame rate */
355*4882a593Smuzhiyun     PIXEL_FORMAT_E enPixFormat; /* RW; Pixel format of the video layer */
356*4882a593Smuzhiyun     RK_BOOL bBypassFrame; /* RW; Whether to bypass frame to video layer */
357*4882a593Smuzhiyun     RK_BOOL bLowDelay; /* RW; Whether start composer at once when channel 0 recive buffer */
358*4882a593Smuzhiyun     COMPRESS_MODE_E enCompressMode; /* RW; Video Layer output compress mode */
359*4882a593Smuzhiyun     DYNAMIC_RANGE_E enDstDynamicRange; /* RW; Video Layer output dynamic range type */
360*4882a593Smuzhiyun } VO_VIDEO_LAYER_ATTR_S;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun typedef struct rkVO_LAYER_PARAM_S {
363*4882a593Smuzhiyun     ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */
364*4882a593Smuzhiyun } VO_LAYER_PARAM_S;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun typedef struct rkVO_ZOOM_RATIO_S {
367*4882a593Smuzhiyun     /*
368*4882a593Smuzhiyun      * RW; Range: [0, 1000]; XRatio = x * 1000 / W,
369*4882a593Smuzhiyun      * x means the start point to be zoomed,
370*4882a593Smuzhiyun      * W means displaying channel's width.
371*4882a593Smuzhiyun      */
372*4882a593Smuzhiyun     RK_U32 u32XRatio;
373*4882a593Smuzhiyun     /*
374*4882a593Smuzhiyun      * RW; Range: [0, 1000]; YRatio = y * 1000 / H,
375*4882a593Smuzhiyun      * y means the start point to be zoomed,
376*4882a593Smuzhiyun      * H means displaying channel's height.
377*4882a593Smuzhiyun      */
378*4882a593Smuzhiyun     RK_U32 u32YRatio;
379*4882a593Smuzhiyun     /*
380*4882a593Smuzhiyun      * RW; Range: [0, 1000]; WRatio = w * 1000 / W,
381*4882a593Smuzhiyun      * w means the width to be zoomed,
382*4882a593Smuzhiyun      * W means displaying channel's width.
383*4882a593Smuzhiyun      */
384*4882a593Smuzhiyun     RK_U32 u32WRatio;
385*4882a593Smuzhiyun     /*
386*4882a593Smuzhiyun      * RW; Range: [0, 1000]; HRatio = h * 1000 / H,
387*4882a593Smuzhiyun      * h means the height to be zoomed,
388*4882a593Smuzhiyun      * H means displaying channel's height.
389*4882a593Smuzhiyun      */
390*4882a593Smuzhiyun     RK_U32 u32HRatio;
391*4882a593Smuzhiyun } VO_ZOOM_RATIO_S;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun typedef struct rkVO_ZOOM_ATTR_S {
394*4882a593Smuzhiyun     VO_ZOOM_IN_E enZoomType; /* choose the type of zoom in */
395*4882a593Smuzhiyun     union {
396*4882a593Smuzhiyun         RECT_S stZoomRect; /* zoom in by rect */
397*4882a593Smuzhiyun         VO_ZOOM_RATIO_S stZoomRatio; /* zoom in by ratio */
398*4882a593Smuzhiyun     };
399*4882a593Smuzhiyun } VO_ZOOM_ATTR_S;
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun typedef struct rkVO_CSC_S {
402*4882a593Smuzhiyun     VO_CSC_MATRIX_E enCscMatrix; /* CSC matrix */
403*4882a593Smuzhiyun     RK_U32 u32Luma; /* RW; Range:    [0, 100]; luminance, default: 50 */
404*4882a593Smuzhiyun     RK_U32 u32Contrast; /* RW; Range:    [0, 100]; contrast, default: 50 */
405*4882a593Smuzhiyun     RK_U32 u32Hue; /* RW; Range:    [0, 100]; hue, default: 50 */
406*4882a593Smuzhiyun     RK_U32 u32Satuature; /* RW; Range:    [0, 100]; satuature, default: 50 */
407*4882a593Smuzhiyun } VO_CSC_S;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun typedef struct rkVO_REGION_INFO_S {
410*4882a593Smuzhiyun     RK_U32 u32RegionNum; /* count of the region */
411*4882a593Smuzhiyun     RECT_S *ATTRIBUTE pstRegion; /* region attribute */
412*4882a593Smuzhiyun } VO_REGION_INFO_S;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun typedef struct rkVO_LAYER_BOUNDARY_S {
415*4882a593Smuzhiyun     RK_U32 u32Width;
416*4882a593Smuzhiyun     RK_U32 u32Color[2];
417*4882a593Smuzhiyun } VO_LAYER_BOUNDARY_S;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun typedef struct rkVO_CHN_BOUNDARY_S {
420*4882a593Smuzhiyun     RK_BOOL bBoundaryEn; /* do Frame or not */
421*4882a593Smuzhiyun     RK_U32 u32ColorIndex; /* the index of Frame color,[0,1] */
422*4882a593Smuzhiyun } VO_CHN_BOUNDARY_S;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun typedef struct rkVO_MOD_PARAM_S {
425*4882a593Smuzhiyun     /*
426*4882a593Smuzhiyun      * RW, Range: [0, 1];  YC(Luminance and Chrominance)
427*4882a593Smuzhiyun      * changes or not when passing through VO
428*4882a593Smuzhiyun      */
429*4882a593Smuzhiyun     RK_BOOL bTransparentTransmit;
430*4882a593Smuzhiyun     RK_BOOL bExitDev;
431*4882a593Smuzhiyun     RK_BOOL bWbcBgBlackEn;
432*4882a593Smuzhiyun     RK_BOOL bDevClkExtEn;
433*4882a593Smuzhiyun     RK_BOOL bSaveBufMode[VO_MAX_PHY_DEV_NUM]; /* save buff mode */
434*4882a593Smuzhiyun } VO_MOD_PARAM_S;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun typedef enum rkVO_CLK_SOURCE_E {
437*4882a593Smuzhiyun     VO_CLK_SOURCE_PLL,
438*4882a593Smuzhiyun     VO_CLK_SOURCE_LCDMCLK,
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun     VO_CLK_SOURCE_BUTT
441*4882a593Smuzhiyun } VO_CLK_SOURCE_E;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun typedef struct rkVO_USER_INTFSYNC_PLL_S {
444*4882a593Smuzhiyun     RK_U32 u32Fbdiv;
445*4882a593Smuzhiyun     RK_U32 u32Frac;
446*4882a593Smuzhiyun     RK_U32 u32Refdiv;
447*4882a593Smuzhiyun     RK_U32 u32Postdiv1;
448*4882a593Smuzhiyun     RK_U32 u32Postdiv2;
449*4882a593Smuzhiyun } VO_USER_INTFSYNC_PLL_S;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun typedef struct rkVO_USER_INTFSYNC_ATTR_S {
452*4882a593Smuzhiyun     VO_CLK_SOURCE_E enClkSource;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun     union {
455*4882a593Smuzhiyun         VO_USER_INTFSYNC_PLL_S stUserSyncPll;
456*4882a593Smuzhiyun         RK_U32 u32LcdMClkDiv;
457*4882a593Smuzhiyun     };
458*4882a593Smuzhiyun } VO_USER_INTFSYNC_ATTR_S;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun typedef struct rkVO_USER_INTFSYNC_INFO_S {
461*4882a593Smuzhiyun     VO_USER_INTFSYNC_ATTR_S stUserIntfSyncAttr;
462*4882a593Smuzhiyun     RK_U32 u32PreDiv;
463*4882a593Smuzhiyun     RK_U32 u32DevDiv;
464*4882a593Smuzhiyun     RK_BOOL bClkReverse;
465*4882a593Smuzhiyun } VO_USER_INTFSYNC_INFO_S;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun typedef struct rkVO_GFX_FRAME_INFO_S {
468*4882a593Smuzhiyun     RK_U32              u32Width;
469*4882a593Smuzhiyun     RK_U32              u32Height;
470*4882a593Smuzhiyun     RK_U32              u32VirWidth;
471*4882a593Smuzhiyun     RK_U32              u32VirHeight;
472*4882a593Smuzhiyun     PIXEL_FORMAT_E      enPixelFormat;
473*4882a593Smuzhiyun     RK_U32              u32FgAlpha;
474*4882a593Smuzhiyun     RK_U32              u32BgAlpha;
475*4882a593Smuzhiyun     RK_VOID             *pData;
476*4882a593Smuzhiyun     RK_U32              u32Size;
477*4882a593Smuzhiyun } VO_FRAME_INFO_S;
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun typedef struct rk_VO_EDID_S {
480*4882a593Smuzhiyun     RK_BOOL             bEdidValid;
481*4882a593Smuzhiyun     RK_U32              u32Edidlength;
482*4882a593Smuzhiyun     RK_U8               u8Edid[512];
483*4882a593Smuzhiyun } VO_EDID_S;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun typedef struct rk_VO_SINK_CAPABILITY_S {
486*4882a593Smuzhiyun     RK_BOOL             bConnected;
487*4882a593Smuzhiyun     RK_BOOL             bSupportYCbCr;
488*4882a593Smuzhiyun     RK_BOOL             bSupportHDMI;
489*4882a593Smuzhiyun } VO_SINK_CAPABILITY_S;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun typedef struct rk_VO_CB_INFO_S {
492*4882a593Smuzhiyun     RK_U32 u32Id;
493*4882a593Smuzhiyun     RK_U32 u32Sec;
494*4882a593Smuzhiyun     RK_U32 u32Usec;
495*4882a593Smuzhiyun } VO_CB_INFO_S;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun /** hpd event handling callback function */
498*4882a593Smuzhiyun typedef void (*RK_VO_CallBack)(RK_VOID *pPrivateData);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun typedef struct rk_VO_CALLBACK_FUNC_S {
501*4882a593Smuzhiyun     RK_VO_CallBack      pfnEventCallback;
502*4882a593Smuzhiyun     RK_VOID             *pPrivateData;
503*4882a593Smuzhiyun } RK_VO_CALLBACK_FUNC_S;
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun /** vsync event handling callback function */
506*4882a593Smuzhiyun typedef void (*RK_VO_VsyncCallBack)(RK_VOID *pPrivateData, VO_CB_INFO_S* info);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun typedef struct rk_VO_VSYNC_CALLBACK_FUNC_S {
509*4882a593Smuzhiyun     RK_VO_VsyncCallBack pfnEventCallback;
510*4882a593Smuzhiyun     RK_VOID             *pPrivateData;
511*4882a593Smuzhiyun } RK_VO_VSYNC_CALLBACK_FUNC_S;
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun typedef enum rkVO_GFX_MODE_E {
514*4882a593Smuzhiyun     VO_MODE_NORMAL,
515*4882a593Smuzhiyun     VO_MODE_GFX_PRE_CREATED
516*4882a593Smuzhiyun } VO_GFX_MODE_E;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun typedef enum rkVO_HDMI_MODE_E {
519*4882a593Smuzhiyun     VO_HDMI_MODE_AUTO = 0,          /* According EDID */
520*4882a593Smuzhiyun     VO_HDMI_MODE_HDMI,
521*4882a593Smuzhiyun     VO_HDMI_MODE_DVI
522*4882a593Smuzhiyun } VO_HDMI_MODE_E;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun typedef enum rkVO_HDMI_COLOR_FMT_E {
525*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMAT_RGB = 0,
526*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMAT_YCBCR444,
527*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMAT_YCBCR422,
528*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMAT_YCBCR420,
529*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMT_AUTO,
530*4882a593Smuzhiyun     VO_HDMI_COLOR_FORMAT_BUTT
531*4882a593Smuzhiyun } VO_HDMI_COLOR_FMT_E;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun typedef enum rkVO_HDMI_QUANT_RANGE_E {
534*4882a593Smuzhiyun     VO_HDMI_QUANT_RANGE_AUTO = 0,   /* Limited: CEA Mode; Full: Non-CEA Mode */
535*4882a593Smuzhiyun     VO_HDMI_QUANT_RANGE_LIMITED,
536*4882a593Smuzhiyun     VO_HDMI_QUANT_RANGE_FULL,
537*4882a593Smuzhiyun     VO_HDMI_QUANT_RANGE_BUTT
538*4882a593Smuzhiyun } VO_HDMI_QUANT_RANGE_E;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun typedef struct rk_VO_HDMI_PARAM_S {
541*4882a593Smuzhiyun     VO_HDMI_MODE_E enHdmiMode;
542*4882a593Smuzhiyun     VO_HDMI_COLOR_FMT_E enColorFmt;
543*4882a593Smuzhiyun     VO_HDMI_QUANT_RANGE_E enQuantRange; /* Effective in enColorFmt == RGB mode */
544*4882a593Smuzhiyun } VO_HDMI_PARAM_S;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun typedef enum rk356X_VO_LAYER_NAME_E {
547*4882a593Smuzhiyun     RK356X_VOP_LAYER_CLUSTER0 = 0,
548*4882a593Smuzhiyun     RK356X_VOP_LAYER_CLUSTER1 = 2,
549*4882a593Smuzhiyun     RK356X_VOP_LAYER_ESMART0  = 4,
550*4882a593Smuzhiyun     RK356X_VOP_LAYER_ESMART1,
551*4882a593Smuzhiyun     RK356X_VOP_LAYER_SMART0,
552*4882a593Smuzhiyun     RK356X_VOP_LAYER_SMART1,
553*4882a593Smuzhiyun } VO_LAYER_NAME_RK356X_E;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun typedef enum rkVOP2_LAYER_NAME_E {
556*4882a593Smuzhiyun     VO_LAYER_CLUSTER0 = 0,
557*4882a593Smuzhiyun     VO_LAYER_CLUSTER1,
558*4882a593Smuzhiyun     VO_LAYER_CLUSTER2,
559*4882a593Smuzhiyun     VO_LAYER_CLUSTER3,
560*4882a593Smuzhiyun     VO_LAYER_ESMART0,
561*4882a593Smuzhiyun     VO_LAYER_ESMART1,
562*4882a593Smuzhiyun     VO_LAYER_ESMART2,
563*4882a593Smuzhiyun     VO_LAYER_ESMART3,
564*4882a593Smuzhiyun     VO_LAYER_BUTT
565*4882a593Smuzhiyun } VO_LAYER_NAME_E;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun typedef enum rkVO_VIR_LAYER_NAME_E {
568*4882a593Smuzhiyun     VO_LAYER_VIRTUAL0 = VO_LAYER_BUTT,
569*4882a593Smuzhiyun     VO_LAYER_VIRTUAL1,
570*4882a593Smuzhiyun     VO_LAYER_VIRTUAL2,
571*4882a593Smuzhiyun     VO_LAYER_VIRTUAL3,
572*4882a593Smuzhiyun } VO_VIR_LAYER_NAME_E;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun #ifdef __cplusplus
575*4882a593Smuzhiyun #if __cplusplus
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun #endif
578*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun #endif /* End of #ifndef INCLUDE_RT_MPI_RK_COMMON_VO_H_ */
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 
583