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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dxlnx,zynqmp-clk.txt2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
3 Zynq MPSoC firmware interface
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
/OK3568_Linux_fs/kernel/drivers/firmware/xilinx/
H A DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
H A Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.txt2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
26 Zynq Ultrascale+ MPSoC
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Dxlnx-rtc.txt1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
3 RTC controller for the Xilinx Zynq MPSoC Real Time Clock
/OK3568_Linux_fs/kernel/drivers/soc/xilinx/
H A DKconfig21 bool "Enable Xilinx Zynq MPSoC Power Management driver"
36 bool "Enable Zynq MPSoC generic PM domains"
H A Dzynqmp_power.c3 * Xilinx Zynq MPSoC Power Management
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Dxlnx,zynqmp-genpd.txt2 Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
9 == Zynq MPSoC Generic PM Domain Node ==
/OK3568_Linux_fs/kernel/Documentation/driver-api/xilinx/
H A Deemi.rst2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
H A Dclk-mux-zynqmp.c3 * Zynq UltraScale+ MPSoC mux
H A Dclk-gate-zynqmp.c3 * Zynq UltraScale+ MPSoC clock controller
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.txt1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dcdns,uart.txt6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-zynqmp.c3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
322 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.txt1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.txt2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
/OK3568_Linux_fs/buildroot/board/zynqmp/
H A Dreadme.txt6 Xilinx, based on the Zynq UltraScale+ MPSoC (aka ZynqMP). It has been
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.txt2 Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h3 * Xilinx Zynq MPSoC Firmware layer
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmacb.txt17 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.txt5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI

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