1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun# Zynq Ultrascale+ MPSoC clock specific Makefile 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunobj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o 5