1*4882a593Smuzhiyun* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRTC controller for the Xilinx Zynq MPSoC Real Time Clock 4*4882a593SmuzhiyunSeparate IRQ lines for seconds and alarm 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: Should be "xlnx,zynqmp-rtc" 8*4882a593Smuzhiyun- reg: Physical base address of the controller and length 9*4882a593Smuzhiyun of memory mapped region. 10*4882a593Smuzhiyun- interrupts: IRQ lines for the RTC. 11*4882a593Smuzhiyun- interrupt-names: interrupt line names eg. "sec" "alarm" 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional: 14*4882a593Smuzhiyun- calibration: calibration value for 1 sec period which will 15*4882a593Smuzhiyun be programmed directly to calibration register 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyunrtc: rtc@ffa60000 { 19*4882a593Smuzhiyun compatible = "xlnx,zynqmp-rtc"; 20*4882a593Smuzhiyun reg = <0x0 0xffa60000 0x100>; 21*4882a593Smuzhiyun interrupt-parent = <&gic>; 22*4882a593Smuzhiyun interrupts = <0 26 4>, <0 27 4>; 23*4882a593Smuzhiyun interrupt-names = "alarm", "sec"; 24*4882a593Smuzhiyun calibration = <0x198233>; 25*4882a593Smuzhiyun}; 26