1*4882a593SmuzhiyunDevicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. 2*4882a593SmuzhiyunThe ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the 3*4882a593SmuzhiyunProgrammable Logic (PL). The configuration uses the firmware interface. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: should contain "xlnx,zynqmp-pcap-fpga" 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunExample for full FPGA configuration: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun fpga-region0 { 11*4882a593Smuzhiyun compatible = "fpga-region"; 12*4882a593Smuzhiyun fpga-mgr = <&zynqmp_pcap>; 13*4882a593Smuzhiyun #address-cells = <0x1>; 14*4882a593Smuzhiyun #size-cells = <0x1>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun firmware { 18*4882a593Smuzhiyun zynqmp_firmware: zynqmp-firmware { 19*4882a593Smuzhiyun compatible = "xlnx,zynqmp-firmware"; 20*4882a593Smuzhiyun method = "smc"; 21*4882a593Smuzhiyun zynqmp_pcap: pcap { 22*4882a593Smuzhiyun compatible = "xlnx,zynqmp-pcap-fpga"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26