1# SPDX-License-Identifier: GPL-2.0 2# Zynq Ultrascale+ MPSoC clock specific Makefile 3 4obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o 5
1# SPDX-License-Identifier: GPL-2.0 2# Zynq Ultrascale+ MPSoC clock specific Makefile 3 4obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o 5