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/OK3568_Linux_fs/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
33 IP core. Please find details on the "Embedded Peripherals IP
41 this Andestech IP core.
50 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
66 SPI core.
79 Enable the Broadcom set-top box SPI driver. This driver can
81 Broadcom SPI core.
86 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
88 Cadence IP core.
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/OK3568_Linux_fs/kernel/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
10 USB controller based on the DesignWare USB3 IP Core.
64 AM437x use this IP for USB2/3 functionality.
73 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
77 tristate "PCIe-based Platforms"
81 If you're using the DesignWare Core IP with a PCIe (but not HAPS
85 tristate "Synopsys PCIe-based HAPS Platforms"
89 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
117 Currently supports Xilinx and Qualcomm DWC USB3 IP.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
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H A Dexample-schema.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
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/OK3568_Linux_fs/yocto/poky/meta/recipes-bsp/grub/files/
H A DCVE-2022-28733-net-ip-Do-IP-fragment-maths-safely.patch4 Subject: [PATCH] net/ip: Do IP fragment maths safely
6 We can receive packets with invalid IP fragmentation information. This
7 can lead to rsm->total_len underflowing and becoming very large.
16 Fixes: CVE-2022-28733
18 Signed-off-by: Daniel Axtens <dja@axtens.net>
19 Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com>
21 Upstream-Status: Backport
22 CVE: CVE-2022-28733
27 Signed-off-by: Yongxin Liu <yongxin.liu@windriver.com>
29 ---
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/OK3568_Linux_fs/kernel/Documentation/driver-api/
H A Dxillybus.rst10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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H A Dxlnx,video.txt1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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/OK3568_Linux_fs/kernel/drivers/staging/axis-fifo/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ptp/
H A Dptp-ines.txt1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dallegro.txt1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
2 ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265
3 decoder ip core.
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
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/OK3568_Linux_fs/kernel/drivers/usb/usbip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB/IP support"
9 This enables pushing USB packets over IP to allow remote
11 USB/IP core that is required by both drivers.
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
39 USB/IP virtual host controller.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.txt2 This file documents differences between the core mmc properties
5 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
19 Require at least input clock for Xenon IP core. For Armada AP806 and
22 - clock-names:
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/OK3568_Linux_fs/kernel/Documentation/networking/caif/
H A Dlinux_caif.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| ST-Ericsson AB 2010
17 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
22 ST-Ericsson modems support a number of transports between modem
31 * CAIF Socket Layer and GPRS IP Interface.
32 * CAIF Core Protocol Implementation
39 ! +------+ +------+
40 ! +------+! +------+!
41 ! ! IP !! !Socket!!
42 +-------> !interf!+ ! API !+ <- CAIF Client APIs
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
68 /* Core enable registers */
84 /* Core ID registers */
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
278 * struct zynqmp_dp - Xilinx DisplayPort core
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/OK3568_Linux_fs/yocto/poky/meta-yocto-bsp/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
20 Note that these reference BSPs use the linux-yocto kernel and in general don't
28 The following boards are supported by the meta-yocto-bsp layer:
30 * Texas Instruments Beaglebone (beaglebone-yocto)
32 * General IA platforms (genericx86 and genericx86-64)
40 Send pull requests, patches, comments or questions about meta-yocto-bsps to poky@lists.yoctoproject…
48 The following consumer devices are supported by the meta-yocto-bsp layer:
65 The genericx86 and genericx86-64 MACHINE are tested on the following platforms:
67 Intel Xeon/Core i-Series:
68 + Intel NUC5 Series - ix-52xx Series SOC (Broadwell)
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/OK3568_Linux_fs/yocto/poky/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
20 Note that these reference BSPs use the linux-yocto kernel and in general don't
28 The following boards are supported by the meta-yocto-bsp layer:
30 * Texas Instruments Beaglebone (beaglebone-yocto)
32 * General IA platforms (genericx86 and genericx86-64)
40 Send pull requests, patches, comments or questions about meta-yocto-bsps to poky@lists.yoctoproject…
48 The following consumer devices are supported by the meta-yocto-bsp layer:
65 The genericx86 and genericx86-64 MACHINE are tested on the following platforms:
67 Intel Xeon/Core i-Series:
68 + Intel NUC5 Series - ix-52xx Series SOC (Broadwell)
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/OK3568_Linux_fs/kernel/tools/perf/util/
H A Dintel-pt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2013-2015, Intel Corporation.
27 #include "thread-stack.h"
34 #include "intel-pt.h"
37 #include "util/synthetic-events.h"
38 #include "time-utils.h"
42 #include "intel-pt-decoder/intel-pt-log.h"
43 #include "intel-pt-decoder/intel-pt-decoder.h"
44 #include "intel-pt-decoder/intel-pt-insn-decoder.h"
45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
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/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
36 This uses the DesignWare core.
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
51 This uses the DesignWare core.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
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/OK3568_Linux_fs/yocto/poky/meta/lib/oeqa/selftest/cases/
H A Druntime_test.py2 # SPDX-License-Identifier: MIT
7 from oeqa.core.decorator import OETestTag
11 from oeqa.core.decorator.data import skipIfNotQemu
22 Product: oe-core
27 # These aren't the actual IP addresses but testexport class needs something defined
33 # Build tesexport for core-image-minimal
34 bitbake('core-image-minimal')
35 bitbake('-c testexport core-image-minimal')
37 testexport_dir = get_bb_var('TEST_EXPORT_DIR', 'core-image-minimal')
43 with runqemu('core-image-minimal') as qemu:
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/OK3568_Linux_fs/yocto/poky/meta/lib/oeqa/controllers/
H A Dcontrollerimage.py3 # SPDX-License-Identifier: MIT
6 # tests using a "controller image" - this is a "known good" image that is
11 # For an example controller image, see core-image-testcontroller
12 # (meta/recipes-extended/images/core-image-testcontroller.bb)
34 # target ip
35 …addr = d.getVar("TEST_TARGET_IP") or bb.fatal('Please set TEST_TARGET_IP with the IP address of th…
36 self.ip = addr.split(":")[0]
41 bb.note("Target IP: %s" % self.ip)
45 …self.server_ip = subprocess.check_output(['ip', 'route', 'get', self.ip ]).split("\n")[0].split()[…
47 …bb.fatal("Failed to determine the host IP address (alternatively you can set TEST_SERVER_IP with t…
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/OK3568_Linux_fs/yocto/poky/meta/lib/oeqa/
H A Drunexported.py5 # SPDX-License-Identifier: MIT
11 #- export the tests:
16 # bitbake core-image-sato -c testimage
17 # Setup your target, e.g for qemu: runqemu core-image-sato
18 # cd build/tmp/testimage/core-image-sato
43 self.ip = None
56 self.connection = SSHControl(self.ip, logfile=self.sshlog)
75 …parser.add_argument("-t", "--target-ip", dest="ip", help="The IP address of the target machine. Us…
77 …parser.add_argument("-s", "--server-ip", dest="server_ip", help="The IP address of this machine. U…
79 …parser.add_argument("-d", "--deploy-dir", dest="deploy_dir", help="Full path to the package feeds,…
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S2 * code for switching cores into non-secure state and into HYP mode
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/proc-armv/ptrace.h>
40 * U-Boot calls this "software interrupt" in start.S
42 * to non-secure state.
44 * ip: target PC
56 push {r0, r1, r2, ip}
58 pop {r0, r1, r2, ip}
97 mov lr, ip
98 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dadi,axi-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Alexandru Ardelean <alexandru.ardelean@analog.com>
14 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
18 interface for the actual ADC, while this IP core will interface
19 to the data-lines of the ADC and handle the streaming of data into
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/OK3568_Linux_fs/kernel/fs/jfs/
H A Djfs_discard.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 * ip - pointer to in-core inode
24 * blkno - starting block number to be trimmed (0..N)
25 * nblocks - number of blocks to be trimmed
32 void jfs_issue_discard(struct inode *ip, u64 blkno, u64 nblocks) in jfs_issue_discard() argument
34 struct super_block *sb = ip->i_sb; in jfs_issue_discard()
58 * ip - pointer to in-core inode;
59 * range - the range, given by user space
62 * 0 - success
63 * -EIO - i/o error
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