1*4882a593SmuzhiyunDevice-tree bindings for the Allegro DVT video IP codecs present in the Xilinx 2*4882a593SmuzhiyunZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265 3*4882a593Smuzhiyundecoder ip core. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunEach actual codec engines is controlled by a microcontroller (MCU). Host 6*4882a593Smuzhiyunsoftware uses a provided mailbox interface to communicate with the MCU. The 7*4882a593SmuzhiyunMCU share an interrupt. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun - compatible: value should be one of the following 11*4882a593Smuzhiyun "allegro,al5e-1.1", "allegro,al5e": encoder IP core 12*4882a593Smuzhiyun "allegro,al5d-1.1", "allegro,al5d": decoder IP core 13*4882a593Smuzhiyun - reg: base and length of the memory mapped register region and base and 14*4882a593Smuzhiyun length of the memory mapped sram 15*4882a593Smuzhiyun - reg-names: must include "regs" and "sram" 16*4882a593Smuzhiyun - interrupts: shared interrupt from the MCUs to the processing system 17*4882a593Smuzhiyun - clocks: must contain an entry for each entry in clock-names 18*4882a593Smuzhiyun - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk", 19*4882a593Smuzhiyun "m_axi_mcu_aclk", "s_axi_lite_aclk" 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun al5e: video-codec@a0009000 { 23*4882a593Smuzhiyun compatible = "allegro,al5e-1.1", "allegro,al5e"; 24*4882a593Smuzhiyun reg = <0 0xa0009000 0 0x1000>, 25*4882a593Smuzhiyun <0 0xa0000000 0 0x8000>; 26*4882a593Smuzhiyun reg-names = "regs", "sram"; 27*4882a593Smuzhiyun interrupts = <0 96 4>; 28*4882a593Smuzhiyun clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>, 29*4882a593Smuzhiyun <&clkc 71>, <&clkc 71>, <&clkc 71>; 30*4882a593Smuzhiyun clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", 31*4882a593Smuzhiyun "m_axi_mcu_aclk", "s_axi_lite_aclk" 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun al5d: video-codec@a0029000 { 34*4882a593Smuzhiyun compatible = "allegro,al5d-1.1", "allegro,al5d"; 35*4882a593Smuzhiyun reg = <0 0xa0029000 0 0x1000>, 36*4882a593Smuzhiyun <0 0xa0020000 0 0x8000>; 37*4882a593Smuzhiyun reg-names = "regs", "sram"; 38*4882a593Smuzhiyun interrupts = <0 96 4>; 39*4882a593Smuzhiyun clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>, 40*4882a593Smuzhiyun <&clkc 71>, <&clkc 71>, <&clkc 71>; 41*4882a593Smuzhiyun clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", 42*4882a593Smuzhiyun "m_axi_mcu_aclk", "s_axi_lite_aclk" 43*4882a593Smuzhiyun }; 44