1*4882a593Smuzhiyunmenuconfig SPI 2*4882a593Smuzhiyun bool "SPI Support" 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunif SPI 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunconfig DM_SPI 7*4882a593Smuzhiyun bool "Enable Driver Model for SPI drivers" 8*4882a593Smuzhiyun depends on DM 9*4882a593Smuzhiyun help 10*4882a593Smuzhiyun Enable driver model for SPI. The SPI slave interface 11*4882a593Smuzhiyun (spi_setup_slave(), spi_xfer(), etc.) is then implemented by 12*4882a593Smuzhiyun the SPI uclass. Drivers provide methods to access the SPI 13*4882a593Smuzhiyun buses that they control. The uclass interface is defined in 14*4882a593Smuzhiyun include/spi.h. The existing spi_slave structure is attached 15*4882a593Smuzhiyun as 'parent data' to every slave on each bus. Slaves 16*4882a593Smuzhiyun typically use driver-private data instead of extending the 17*4882a593Smuzhiyun spi_slave structure. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig SPI_MEM 20*4882a593Smuzhiyun bool "SPI memory extension" 21*4882a593Smuzhiyun help 22*4882a593Smuzhiyun Enable this option if you want to enable the SPI memory extension. 23*4882a593Smuzhiyun This extension is meant to simplify interaction with SPI memories 24*4882a593Smuzhiyun by providing an high-level interface to send memory-like commands. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunif DM_SPI 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunconfig ALTERA_SPI 29*4882a593Smuzhiyun bool "Altera SPI driver" 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun Enable the Altera SPI driver. This driver can be used to 32*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Altera 33*4882a593Smuzhiyun IP core. Please find details on the "Embedded Peripherals IP 34*4882a593Smuzhiyun User Guide" of Altera. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig ATCSPI200_SPI 37*4882a593Smuzhiyun bool "Andestech ATCSPI200 SPI driver" 38*4882a593Smuzhiyun help 39*4882a593Smuzhiyun Enable the Andestech ATCSPI200 SPI driver. This driver can be 40*4882a593Smuzhiyun used to access the SPI flash on AE3XX and AE250 platforms embedding 41*4882a593Smuzhiyun this Andestech IP core. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunconfig ATH79_SPI 44*4882a593Smuzhiyun bool "Atheros SPI driver" 45*4882a593Smuzhiyun depends on ARCH_ATH79 46*4882a593Smuzhiyun help 47*4882a593Smuzhiyun Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used 48*4882a593Smuzhiyun to access SPI NOR flash and other SPI peripherals. This driver 49*4882a593Smuzhiyun uses driver model and requires a device tree binding to operate. 50*4882a593Smuzhiyun please refer to doc/device-tree-bindings/spi/spi-ath79.txt. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunconfig ATMEL_SPI 53*4882a593Smuzhiyun bool "Atmel SPI driver" 54*4882a593Smuzhiyun default y if ARCH_AT91 55*4882a593Smuzhiyun help 56*4882a593Smuzhiyun This enables driver for the Atmel SPI Controller, present on 57*4882a593Smuzhiyun many AT91 (ARM) chips. This driver can be used to access 58*4882a593Smuzhiyun the SPI Flash, such as AT25DF321. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunconfig BCM63XX_HSSPI 61*4882a593Smuzhiyun bool "BCM63XX HSSPI driver" 62*4882a593Smuzhiyun depends on ARCH_BMIPS 63*4882a593Smuzhiyun help 64*4882a593Smuzhiyun Enable the BCM6328 HSSPI driver. This driver can be used to 65*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Broadcom 66*4882a593Smuzhiyun SPI core. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunconfig BCM63XX_SPI 69*4882a593Smuzhiyun bool "BCM6348 SPI driver" 70*4882a593Smuzhiyun depends on ARCH_BMIPS 71*4882a593Smuzhiyun help 72*4882a593Smuzhiyun Enable the BCM6348/BCM6358 SPI driver. This driver can be used to 73*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding these Broadcom 74*4882a593Smuzhiyun SPI cores. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunconfig BCMSTB_SPI 77*4882a593Smuzhiyun bool "BCMSTB SPI driver" 78*4882a593Smuzhiyun help 79*4882a593Smuzhiyun Enable the Broadcom set-top box SPI driver. This driver can 80*4882a593Smuzhiyun be used to access the SPI flash on platforms embedding this 81*4882a593Smuzhiyun Broadcom SPI core. 82*4882a593Smuzhiyun 83*4882a593Smuzhiyunconfig CADENCE_QSPI 84*4882a593Smuzhiyun bool "Cadence QSPI driver" 85*4882a593Smuzhiyun help 86*4882a593Smuzhiyun Enable the Cadence Quad-SPI (QSPI) driver. This driver can be 87*4882a593Smuzhiyun used to access the SPI NOR flash on platforms embedding this 88*4882a593Smuzhiyun Cadence IP core. 89*4882a593Smuzhiyun 90*4882a593Smuzhiyunconfig DESIGNWARE_SPI 91*4882a593Smuzhiyun bool "Designware SPI driver" 92*4882a593Smuzhiyun help 93*4882a593Smuzhiyun Enable the Designware SPI driver. This driver can be used to 94*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Designware 95*4882a593Smuzhiyun IP core. 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunconfig EXYNOS_SPI 98*4882a593Smuzhiyun bool "Samsung Exynos SPI driver" 99*4882a593Smuzhiyun help 100*4882a593Smuzhiyun Enable the Samsung Exynos SPI driver. This driver can be used to 101*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Samsung 102*4882a593Smuzhiyun Exynos IP core. 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunconfig FSL_DSPI 105*4882a593Smuzhiyun bool "Freescale DSPI driver" 106*4882a593Smuzhiyun help 107*4882a593Smuzhiyun Enable the Freescale DSPI driver. This driver can be used to 108*4882a593Smuzhiyun access the SPI NOR flash and SPI Data flash on platforms embedding 109*4882a593Smuzhiyun this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms 110*4882a593Smuzhiyun use this driver. 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunconfig ICH_SPI 113*4882a593Smuzhiyun bool "Intel ICH SPI driver" 114*4882a593Smuzhiyun help 115*4882a593Smuzhiyun Enable the Intel ICH SPI driver. This driver can be used to 116*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Intel 117*4882a593Smuzhiyun ICH IP core. 118*4882a593Smuzhiyun 119*4882a593Smuzhiyunconfig MVEBU_A3700_SPI 120*4882a593Smuzhiyun bool "Marvell Armada 3700 SPI driver" 121*4882a593Smuzhiyun help 122*4882a593Smuzhiyun Enable the Marvell Armada 3700 SPI driver. This driver can be 123*4882a593Smuzhiyun used to access the SPI NOR flash on platforms embedding this 124*4882a593Smuzhiyun Marvell IP core. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyunconfig PIC32_SPI 127*4882a593Smuzhiyun bool "Microchip PIC32 SPI driver" 128*4882a593Smuzhiyun depends on MACH_PIC32 129*4882a593Smuzhiyun help 130*4882a593Smuzhiyun Enable the Microchip PIC32 SPI driver. This driver can be used 131*4882a593Smuzhiyun to access the SPI NOR flash, MMC-over-SPI on platforms based on 132*4882a593Smuzhiyun Microchip PIC32 family devices. 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunconfig RENESAS_RPC_SPI 135*4882a593Smuzhiyun bool "Renesas RPC SPI driver" 136*4882a593Smuzhiyun depends on RCAR_GEN3 137*4882a593Smuzhiyun help 138*4882a593Smuzhiyun Enable the Renesas RPC SPI driver, used to access SPI NOR flash 139*4882a593Smuzhiyun on Renesas RCar Gen3 SoCs. This uses driver model and requires a 140*4882a593Smuzhiyun device tree binding to operate. 141*4882a593Smuzhiyun 142*4882a593Smuzhiyunconfig ROCKCHIP_SPI 143*4882a593Smuzhiyun bool "Rockchip SPI driver" 144*4882a593Smuzhiyun help 145*4882a593Smuzhiyun Enable the Rockchip SPI driver, used to access SPI NOR flash and 146*4882a593Smuzhiyun other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. 147*4882a593Smuzhiyun This uses driver model and requires a device tree binding to 148*4882a593Smuzhiyun operate. 149*4882a593Smuzhiyun 150*4882a593Smuzhiyunconfig ROCKCHIP_SFC 151*4882a593Smuzhiyun bool "Rockchip SFC driver" 152*4882a593Smuzhiyun help 153*4882a593Smuzhiyun Enable the Rockchip SFC driver, used to access SPI NOR flash 154*4882a593Smuzhiyun on Rockchip SoCs. 155*4882a593Smuzhiyun This uses driver model and requires a device tree binding to 156*4882a593Smuzhiyun operate. 157*4882a593Smuzhiyun 158*4882a593Smuzhiyunconfig SANDBOX_SPI 159*4882a593Smuzhiyun bool "Sandbox SPI driver" 160*4882a593Smuzhiyun depends on SANDBOX && DM 161*4882a593Smuzhiyun help 162*4882a593Smuzhiyun Enable SPI support for sandbox. This is an emulation of a real SPI 163*4882a593Smuzhiyun bus. Devices can be attached to the bus using the device tree 164*4882a593Smuzhiyun which specifies the driver to use. As an example, see this device 165*4882a593Smuzhiyun tree fragment from sandbox.dts. It shows that the SPI bus has a 166*4882a593Smuzhiyun single flash device on chip select 0 which is emulated by the driver 167*4882a593Smuzhiyun for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun spi@0 { 170*4882a593Smuzhiyun #address-cells = <1>; 171*4882a593Smuzhiyun #size-cells = <0>; 172*4882a593Smuzhiyun reg = <0>; 173*4882a593Smuzhiyun compatible = "sandbox,spi"; 174*4882a593Smuzhiyun cs-gpios = <0>, <&gpio_a 0>; 175*4882a593Smuzhiyun flash@0 { 176*4882a593Smuzhiyun reg = <0>; 177*4882a593Smuzhiyun compatible = "spansion,m25p16", "sandbox,spi-flash"; 178*4882a593Smuzhiyun spi-max-frequency = <40000000>; 179*4882a593Smuzhiyun sandbox,filename = "spi.bin"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyunconfig STM32_QSPI 184*4882a593Smuzhiyun bool "STM32F7 QSPI driver" 185*4882a593Smuzhiyun depends on STM32F7 186*4882a593Smuzhiyun help 187*4882a593Smuzhiyun Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be 188*4882a593Smuzhiyun used to access the SPI NOR flash chips on platforms embedding 189*4882a593Smuzhiyun this ST IP core. 190*4882a593Smuzhiyun 191*4882a593Smuzhiyunconfig TEGRA114_SPI 192*4882a593Smuzhiyun bool "nVidia Tegra114 SPI driver" 193*4882a593Smuzhiyun help 194*4882a593Smuzhiyun Enable the nVidia Tegra114 SPI driver. This driver can be used to 195*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this nVidia Tegra114 196*4882a593Smuzhiyun IP core. 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun This controller is different than the older SoCs SPI controller and 199*4882a593Smuzhiyun also register interface get changed with this controller. 200*4882a593Smuzhiyun 201*4882a593Smuzhiyunconfig TEGRA20_SFLASH 202*4882a593Smuzhiyun bool "nVidia Tegra20 Serial Flash controller driver" 203*4882a593Smuzhiyun help 204*4882a593Smuzhiyun Enable the nVidia Tegra20 Serial Flash controller driver. This driver 205*4882a593Smuzhiyun can be used to access the SPI NOR flash on platforms embedding this 206*4882a593Smuzhiyun nVidia Tegra20 IP core. 207*4882a593Smuzhiyun 208*4882a593Smuzhiyunconfig TEGRA20_SLINK 209*4882a593Smuzhiyun bool "nVidia Tegra20/Tegra30 SLINK driver" 210*4882a593Smuzhiyun help 211*4882a593Smuzhiyun Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can 212*4882a593Smuzhiyun be used to access the SPI NOR flash on platforms embedding this 213*4882a593Smuzhiyun nVidia Tegra20/Tegra30 IP cores. 214*4882a593Smuzhiyun 215*4882a593Smuzhiyunconfig TEGRA210_QSPI 216*4882a593Smuzhiyun bool "nVidia Tegra210 QSPI driver" 217*4882a593Smuzhiyun help 218*4882a593Smuzhiyun Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver 219*4882a593Smuzhiyun be used to access SPI chips on platforms embedding this 220*4882a593Smuzhiyun NVIDIA Tegra210 IP core. 221*4882a593Smuzhiyun 222*4882a593Smuzhiyunconfig XILINX_SPI 223*4882a593Smuzhiyun bool "Xilinx SPI driver" 224*4882a593Smuzhiyun help 225*4882a593Smuzhiyun Enable the Xilinx SPI driver from the Xilinx EDK. This SPI 226*4882a593Smuzhiyun controller support 8 bit SPI transfers only, with or w/o FIFO. 227*4882a593Smuzhiyun For more info on Xilinx SPI Register Definitions and Overview 228*4882a593Smuzhiyun see driver file - drivers/spi/xilinx_spi.c 229*4882a593Smuzhiyun 230*4882a593Smuzhiyunconfig ZYNQ_SPI 231*4882a593Smuzhiyun bool "Zynq SPI driver" 232*4882a593Smuzhiyun depends on ARCH_ZYNQ || ARCH_ZYNQMP 233*4882a593Smuzhiyun help 234*4882a593Smuzhiyun Enable the Zynq SPI driver. This driver can be used to 235*4882a593Smuzhiyun access the SPI NOR flash on platforms embedding this Zynq 236*4882a593Smuzhiyun SPI IP core. 237*4882a593Smuzhiyun 238*4882a593Smuzhiyunconfig ZYNQ_QSPI 239*4882a593Smuzhiyun bool "Zynq QSPI driver" 240*4882a593Smuzhiyun depends on ARCH_ZYNQ 241*4882a593Smuzhiyun help 242*4882a593Smuzhiyun Enable the Zynq Quad-SPI (QSPI) driver. This driver can be 243*4882a593Smuzhiyun used to access the SPI NOR flash on platforms embedding this 244*4882a593Smuzhiyun Zynq QSPI IP core. This IP is used to connect the flash in 245*4882a593Smuzhiyun 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. 246*4882a593Smuzhiyun 247*4882a593Smuzhiyunendif # if DM_SPI 248*4882a593Smuzhiyun 249*4882a593Smuzhiyunconfig SOFT_SPI 250*4882a593Smuzhiyun bool "Soft SPI driver" 251*4882a593Smuzhiyun help 252*4882a593Smuzhiyun Enable Soft SPI driver. This driver is to use GPIO simulate 253*4882a593Smuzhiyun the SPI protocol. 254*4882a593Smuzhiyun 255*4882a593Smuzhiyunconfig CF_SPI 256*4882a593Smuzhiyun bool "ColdFire SPI driver" 257*4882a593Smuzhiyun help 258*4882a593Smuzhiyun Enable the ColdFire SPI driver. This driver can be used on 259*4882a593Smuzhiyun some m68k SoCs. 260*4882a593Smuzhiyun 261*4882a593Smuzhiyunconfig FSL_ESPI 262*4882a593Smuzhiyun bool "Freescale eSPI driver" 263*4882a593Smuzhiyun help 264*4882a593Smuzhiyun Enable the Freescale eSPI driver. This driver can be used to 265*4882a593Smuzhiyun access the SPI interface and SPI NOR flash on platforms embedding 266*4882a593Smuzhiyun this Freescale eSPI IP core. 267*4882a593Smuzhiyun 268*4882a593Smuzhiyunconfig FSL_QSPI 269*4882a593Smuzhiyun bool "Freescale QSPI driver" 270*4882a593Smuzhiyun help 271*4882a593Smuzhiyun Enable the Freescale Quad-SPI (QSPI) driver. This driver can be 272*4882a593Smuzhiyun used to access the SPI NOR flash on platforms embedding this 273*4882a593Smuzhiyun Freescale IP core. 274*4882a593Smuzhiyun 275*4882a593Smuzhiyunconfig DAVINCI_SPI 276*4882a593Smuzhiyun bool "Davinci & Keystone SPI driver" 277*4882a593Smuzhiyun depends on ARCH_DAVINCI || ARCH_KEYSTONE 278*4882a593Smuzhiyun help 279*4882a593Smuzhiyun Enable the Davinci SPI driver 280*4882a593Smuzhiyun 281*4882a593Smuzhiyunconfig SH_SPI 282*4882a593Smuzhiyun bool "SuperH SPI driver" 283*4882a593Smuzhiyun help 284*4882a593Smuzhiyun Enable the SuperH SPI controller driver. This driver can be used 285*4882a593Smuzhiyun on various SuperH SoCs, such as SH7757. 286*4882a593Smuzhiyun 287*4882a593Smuzhiyunconfig SH_QSPI 288*4882a593Smuzhiyun bool "Renesas Quad SPI driver" 289*4882a593Smuzhiyun help 290*4882a593Smuzhiyun Enable the Renesas Quad SPI controller driver. This driver can be 291*4882a593Smuzhiyun used on Renesas SoCs. 292*4882a593Smuzhiyun 293*4882a593Smuzhiyunconfig TI_QSPI 294*4882a593Smuzhiyun bool "TI QSPI driver" 295*4882a593Smuzhiyun help 296*4882a593Smuzhiyun Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. 297*4882a593Smuzhiyun This driver support spi flash single, quad and memory reads. 298*4882a593Smuzhiyun 299*4882a593Smuzhiyunconfig KIRKWOOD_SPI 300*4882a593Smuzhiyun bool "Marvell Kirkwood SPI Driver" 301*4882a593Smuzhiyun help 302*4882a593Smuzhiyun Enable support for SPI on various Marvell SoCs, such as 303*4882a593Smuzhiyun Kirkwood and Armada 375. 304*4882a593Smuzhiyun 305*4882a593Smuzhiyunconfig LPC32XX_SSP 306*4882a593Smuzhiyun bool "LPC32XX SPI Driver" 307*4882a593Smuzhiyun help 308*4882a593Smuzhiyun Enable support for SPI on LPC32xx 309*4882a593Smuzhiyun 310*4882a593Smuzhiyunconfig MPC8XX_SPI 311*4882a593Smuzhiyun bool "MPC8XX SPI Driver" 312*4882a593Smuzhiyun depends on MPC8xx 313*4882a593Smuzhiyun help 314*4882a593Smuzhiyun Enable support for SPI on MPC8XX 315*4882a593Smuzhiyun 316*4882a593Smuzhiyunconfig MPC8XXX_SPI 317*4882a593Smuzhiyun bool "MPC8XXX SPI Driver" 318*4882a593Smuzhiyun help 319*4882a593Smuzhiyun Enable support for SPI on the MPC8XXX PowerPC SoCs. 320*4882a593Smuzhiyun 321*4882a593Smuzhiyunconfig MXC_SPI 322*4882a593Smuzhiyun bool "MXC SPI Driver" 323*4882a593Smuzhiyun help 324*4882a593Smuzhiyun Enable the MXC SPI controller driver. This driver can be used 325*4882a593Smuzhiyun on various i.MX SoCs such as i.MX31/35/51/6/7. 326*4882a593Smuzhiyun 327*4882a593Smuzhiyunconfig MXS_SPI 328*4882a593Smuzhiyun bool "MXS SPI Driver" 329*4882a593Smuzhiyun help 330*4882a593Smuzhiyun Enable the MXS SPI controller driver. This driver can be used 331*4882a593Smuzhiyun on the i.MX23 and i.MX28 SoCs. 332*4882a593Smuzhiyun 333*4882a593Smuzhiyunconfig OMAP3_SPI 334*4882a593Smuzhiyun bool "McSPI driver for OMAP" 335*4882a593Smuzhiyun help 336*4882a593Smuzhiyun SPI master controller for OMAP24XX and later Multichannel SPI 337*4882a593Smuzhiyun (McSPI). This driver be used to access SPI chips on platforms 338*4882a593Smuzhiyun embedding this OMAP3 McSPI IP core. 339*4882a593Smuzhiyun 340*4882a593Smuzhiyunendif # menu "SPI Support" 341