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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
51 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
64 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
107 /* Relative to priv->regmap */
109 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
128 * A lane is described by the following bitfields:
[all …]
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
41 #define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
42 #define COMPHY_FW_SPEED_2_5G 1
58 unsigned int lane; member
67 .lane = _lane, \
81 /* lane 0 */
84 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
86 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
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/OK3568_Linux_fs/kernel/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
62 unsigned int lpd; /* RCW lane powerdown bit */
66 { 1, 153, FSL_SRDS_BANK_1 },
96 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
98 return lanes[lane].idx; in serdes_get_lane_idx()
101 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
106 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
[all …]
H A Dmpc8536_serdes.c5 * SPDX-License-Identifier: GPL-2.0+
76 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
79 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
84 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
87 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
97 int lane; in fsl_serdes_init() local
99 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
100 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
114 case 1: /* Lane A - SATA1, Lane E - SATA2 */ in fsl_serdes_init()
122 /* CR 1 */ in fsl_serdes_init()
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H A Dp1010_serdes.c5 * SPDX-License-Identifier: GPL-2.0+
38 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
41 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
46 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
49 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
55 u32 pordevsr = in_be32(&gur->pordevsr); in fsl_serdes_init()
58 int lane; in fsl_serdes_init() local
60 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
61 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h4 * SPDX-License-Identifier: GPL-2.0
28 PEX_BUS_MODE_X1 = 1,
56 * Bus speed - one bit per SERDES line:
57 * Low speed (0) High speed (1)
69 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
70 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
71 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
72 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
73 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
74 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
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/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
56 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
57 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
58 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
59 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
61 (1 << (1 + (x) * 3))
62 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
65 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
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/OK3568_Linux_fs/u-boot/board/highbank/
H A Dahci.c4 * SPDX-License-Identifier: GPL-2.0+
82 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
85 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
87 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
90 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
94 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
97 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
103 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
110 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
112 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_mux.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
16 * is valid for specific lane. If the type is not valid,
17 * the function update the struct and set the type of the lane as
24 int lane, opt, valid; in comphy_mux_check_config() local
28 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
29 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
31 if (comphy_map_data->type == PHY_TYPE_IGNORE) in comphy_mux_check_config()
34 mux_opt = mux_data->mux_values; in comphy_mux_check_config()
35 for (opt = 0, valid = 0; opt < mux_data->max_lane_values; in comphy_mux_check_config()
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H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
[all …]
H A Dcomphy_core.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
6 * SPDX-License-Identifier: GPL-2.0+
50 debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ", in reg_set()
69 debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ", in reg_set16()
89 u32 lane; in comphy_print() local
91 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
92 lane++, comphy_map_data++) { in comphy_print()
93 if (comphy_map_data->speed == PHY_SPEED_INVALID) { in comphy_print()
94 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
95 get_type_string(comphy_map_data->type)); in comphy_print()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch-rockchip/clock.h>
32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
98 int lane, lane_count, retval; in analogix_dp_link_start() local
100 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
102 dp->link_train.lt_state = CLOCK_RECOVERY; in analogix_dp_link_start()
103 dp->link_train.eq_loop = 0; in analogix_dp_link_start()
105 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
106 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c19 link->ctx->logger
38 /* to avoid infinite loop where-in the receiver
78 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
79 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval()
113 1); in dpcd_set_training_pattern()
133 struct encoder_feature_support *features = &link->link_enc->features; in decide_eq_training_pattern()
134 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern()
136 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern()
139 if (features->flags.bits.IS_TPS4_CAPABLE) in decide_eq_training_pattern()
142 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in decide_eq_training_pattern()
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/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
151 #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
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/OK3568_Linux_fs/u-boot/board/freescale/t1040qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
35 * means that the mapping must be determined dynamically, or that the lane
55 #define EMI1_RGMII1 1
121 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
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/OK3568_Linux_fs/u-boot/board/freescale/ls1043aqds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
24 #define EMI1_RGMII2 1
44 static u8 lane_to_slot[] = {1, 2, 3, 4};
96 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
98 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
100 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
106 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
108 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_write()
110 return priv->realbus->write(priv->realbus, addr, devad, in ls1043aqds_mdio_write()
116 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_reset()
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/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
14 * and 5 1G interfaces and 10G interface per FMan. Based on the options in
15 * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
31 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
44 * 1) An alias for each PHY node that an Ethernet node could be routed to.
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/p2041rdb/
H A Deth.c5 * SPDX-License-Identifier: GPL-2.0+
9 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
10 * are provided by the three on-board PHY or by the standard Freescale
11 * four-port SGMII riser card. We need to change the phy-handle in the
30 * that the mapping must be determined dynamically, or that the lane maps to
34 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
53 lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; in initialize_lane_to_slot()
62 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
67 * ... update the phy-handle property of the Ethernet node to point to the
75 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c4 * SPDX-License-Identifier: GPL-2.0+
34 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
37 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
42 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
45 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
51 ccsr_gur_t *gur = &immap->im_gur; in fsl_serdes_init()
52 u32 pordevsr = in_be32(&gur->pordevsr); in fsl_serdes_init()
55 int lane; in fsl_serdes_init() local
57 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
58 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-combphy.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <dt-bindings/phy/phy.h>
28 PHY_POR_RSTN = 1,
97 return "otg-rst"; in get_reset_name()
99 return "combphy-por"; in get_reset_name()
101 return "combphy-apb"; in get_reset_name()
103 return "combphy-pipe"; in get_reset_name()
117 ret = regmap_read(base, reg->offset, &orig); in param_read()
121 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
122 tmp = (orig & mask) >> reg->bitstart; in param_read()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "xusb-padctl-common.h"
18 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare()
19 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare()
21 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare()
26 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable()
27 return phy->ops->enable(phy); in tegra_xusb_phy_enable()
29 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]

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