1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <config.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/immap_86xx.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SRDS1_MAX_LANES 4
14*4882a593Smuzhiyun #define SRDS2_MAX_LANES 4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19*4882a593Smuzhiyun [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
20*4882a593Smuzhiyun [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
21*4882a593Smuzhiyun [0x7] = {NONE, NONE, NONE, NONE},
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
25*4882a593Smuzhiyun [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
26*4882a593Smuzhiyun [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
27*4882a593Smuzhiyun [0x7] = {NONE, NONE, NONE, NONE},
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
is_serdes_configured(enum srds_prtcl device)30*4882a593Smuzhiyun int is_serdes_configured(enum srds_prtcl device)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun int ret;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (!(serdes1_prtcl_map & (1 << NONE)))
35*4882a593Smuzhiyun fsl_serdes_init();
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun ret = (1 << device) & serdes1_prtcl_map;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (ret)
40*4882a593Smuzhiyun return ret;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (!(serdes2_prtcl_map & (1 << NONE)))
43*4882a593Smuzhiyun fsl_serdes_init();
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return (1 << device) & serdes2_prtcl_map;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
fsl_serdes_init(void)48*4882a593Smuzhiyun void fsl_serdes_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
51*4882a593Smuzhiyun ccsr_gur_t *gur = &immap->im_gur;
52*4882a593Smuzhiyun u32 pordevsr = in_be32(&gur->pordevsr);
53*4882a593Smuzhiyun u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
54*4882a593Smuzhiyun MPC8610_PORDEVSR_IO_SEL_SHIFT;
55*4882a593Smuzhiyun int lane;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (serdes1_prtcl_map & (1 << NONE) &&
58*4882a593Smuzhiyun serdes2_prtcl_map & (1 << NONE))
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
64*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
65*4882a593Smuzhiyun return;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
68*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
69*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << lane_prtcl);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
73*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << NONE);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
76*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
77*4882a593Smuzhiyun return;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
81*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
82*4882a593Smuzhiyun serdes2_prtcl_map |= (1 << lane_prtcl);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
86*4882a593Smuzhiyun serdes2_prtcl_map |= (1 << NONE);
87*4882a593Smuzhiyun }
88