1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Marvell International Ltd.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "comphy.h"
11*4882a593Smuzhiyun #include "comphy_hpipe.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * comphy_mux_check_config()
15*4882a593Smuzhiyun * description: this function passes over the COMPHY lanes and check if the type
16*4882a593Smuzhiyun * is valid for specific lane. If the type is not valid,
17*4882a593Smuzhiyun * the function update the struct and set the type of the lane as
18*4882a593Smuzhiyun * PHY_TYPE_UNCONNECTED
19*4882a593Smuzhiyun */
comphy_mux_check_config(struct comphy_mux_data * mux_data,struct comphy_map * comphy_map_data,int comphy_max_lanes)20*4882a593Smuzhiyun static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
21*4882a593Smuzhiyun struct comphy_map *comphy_map_data, int comphy_max_lanes)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct comphy_mux_options *mux_opt;
24*4882a593Smuzhiyun int lane, opt, valid;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun debug_enter();
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun for (lane = 0; lane < comphy_max_lanes;
29*4882a593Smuzhiyun lane++, comphy_map_data++, mux_data++) {
30*4882a593Smuzhiyun /* Don't check ignored COMPHYs */
31*4882a593Smuzhiyun if (comphy_map_data->type == PHY_TYPE_IGNORE)
32*4882a593Smuzhiyun continue;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun mux_opt = mux_data->mux_values;
35*4882a593Smuzhiyun for (opt = 0, valid = 0; opt < mux_data->max_lane_values;
36*4882a593Smuzhiyun opt++, mux_opt++) {
37*4882a593Smuzhiyun if (mux_opt->type == comphy_map_data->type) {
38*4882a593Smuzhiyun valid = 1;
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun if (valid == 0) {
43*4882a593Smuzhiyun debug("lane number %d, had invalid type %d\n",
44*4882a593Smuzhiyun lane, comphy_map_data->type);
45*4882a593Smuzhiyun debug("set lane %d as type %d\n", lane,
46*4882a593Smuzhiyun PHY_TYPE_UNCONNECTED);
47*4882a593Smuzhiyun comphy_map_data->type = PHY_TYPE_UNCONNECTED;
48*4882a593Smuzhiyun } else {
49*4882a593Smuzhiyun debug("lane number %d, has type %d\n",
50*4882a593Smuzhiyun lane, comphy_map_data->type);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun debug_exit();
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
comphy_mux_get_mux_value(struct comphy_mux_data * mux_data,u32 type,int lane)57*4882a593Smuzhiyun static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data,
58*4882a593Smuzhiyun u32 type, int lane)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct comphy_mux_options *mux_opt;
61*4882a593Smuzhiyun int opt;
62*4882a593Smuzhiyun u32 value = 0;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun debug_enter();
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun mux_opt = mux_data->mux_values;
67*4882a593Smuzhiyun for (opt = 0 ; opt < mux_data->max_lane_values; opt++, mux_opt++) {
68*4882a593Smuzhiyun if (mux_opt->type == type) {
69*4882a593Smuzhiyun value = mux_opt->mux_value;
70*4882a593Smuzhiyun break;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun debug_exit();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return value;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
comphy_mux_reg_write(struct comphy_mux_data * mux_data,struct comphy_map * comphy_map_data,int comphy_max_lanes,void __iomem * selector_base,u32 bitcount)79*4882a593Smuzhiyun static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
80*4882a593Smuzhiyun struct comphy_map *comphy_map_data,
81*4882a593Smuzhiyun int comphy_max_lanes,
82*4882a593Smuzhiyun void __iomem *selector_base, u32 bitcount)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun u32 lane, value, offset, mask;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun debug_enter();
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun for (lane = 0; lane < comphy_max_lanes;
89*4882a593Smuzhiyun lane++, comphy_map_data++, mux_data++) {
90*4882a593Smuzhiyun if (comphy_map_data->type == PHY_TYPE_IGNORE)
91*4882a593Smuzhiyun continue;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun offset = lane * bitcount;
94*4882a593Smuzhiyun mask = (((1 << bitcount) - 1) << offset);
95*4882a593Smuzhiyun value = (comphy_mux_get_mux_value(mux_data,
96*4882a593Smuzhiyun comphy_map_data->type,
97*4882a593Smuzhiyun lane) << offset);
98*4882a593Smuzhiyun reg_set(selector_base, value, mask);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun debug_exit();
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
comphy_mux_init(struct chip_serdes_phy_config * chip_cfg,struct comphy_map * comphy_map_data,void __iomem * selector_base)104*4882a593Smuzhiyun void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg,
105*4882a593Smuzhiyun struct comphy_map *comphy_map_data,
106*4882a593Smuzhiyun void __iomem *selector_base)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct comphy_mux_data *mux_data;
109*4882a593Smuzhiyun u32 mux_bitcount;
110*4882a593Smuzhiyun u32 comphy_max_lanes;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun debug_enter();
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun comphy_max_lanes = chip_cfg->comphy_lanes_count;
115*4882a593Smuzhiyun mux_data = chip_cfg->mux_data;
116*4882a593Smuzhiyun mux_bitcount = chip_cfg->comphy_mux_bitcount;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* check if the configuration is valid */
119*4882a593Smuzhiyun comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes);
120*4882a593Smuzhiyun /* Init COMPHY selectors */
121*4882a593Smuzhiyun comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes,
122*4882a593Smuzhiyun selector_base, mux_bitcount);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun debug_exit();
125*4882a593Smuzhiyun }
126