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12

/OK3568_Linux_fs/u-boot/board/terasic/de0-nano-soc/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
13 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
19 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
36 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
45 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
46 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
[all …]
/OK3568_Linux_fs/u-boot/board/ebv/socrates/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/terasic/sockit/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/aries/mcvevk/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/samtec/vining_fpga/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/sr1500/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/is1/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/terasic/de1-soc/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/altera/cyclone5-socdk/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/OK3568_Linux_fs/u-boot/board/terasic/de10-nano/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/OK3568_Linux_fs/u-boot/board/altera/arria5-socdk/qts/
H A Dsdram_config.h11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dlt6911uxc.h11 #define LT6911UXC_FW_VERSION 0x2005
12 #define LT6911UXC_CHIPID 0x0417
14 #define I2C_ENABLE 0x1
15 #define I2C_DISABLE 0x0
17 #define AD_LMTX_WRITE_CLK 0x1b
21 #define I2C_EN_REG 0x80EE
23 #define CHIPID_H 0x8101
24 #define CHIPID_L 0x8100
25 #define FW_VER_A 0x86a7
26 #define FW_VER_B 0x86a8
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Damlogic,meson-saradc.yaml129 reg = <0x0 0x8680 0x0 0x34>;
140 reg = <0x0 0x9680 0x0 0x34>;
/OK3568_Linux_fs/kernel/include/video/
H A Dpermedia2.h17 #define PM2_REGS_SIZE 0x10000
19 #define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
25 #define PM2R_RESET_STATUS 0x0000
26 #define PM2R_IN_FIFO_SPACE 0x0018
27 #define PM2R_OUT_FIFO_WORDS 0x0020
28 #define PM2R_APERTURE_ONE 0x0050
29 #define PM2R_APERTURE_TWO 0x0058
30 #define PM2R_FIFO_DISCON 0x0068
31 #define PM2R_CHIP_CONFIG 0x0070
33 #define PM2R_REBOOT 0x1000
[all …]
H A Dpm3fb.h19 #define PM3ResetStatus 0x0000
20 #define PM3IntEnable 0x0008
21 #define PM3IntFlags 0x0010
22 #define PM3InFIFOSpace 0x0018
23 #define PM3OutFIFOWords 0x0020
24 #define PM3DMAAddress 0x0028
25 #define PM3DMACount 0x0030
26 #define PM3ErrorFlags 0x0038
27 #define PM3VClkCtl 0x0040
28 #define PM3TestRegister 0x0048
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmeson.dtsi22 reg = <0xc1100000 0x200000>;
25 ranges = <0x0 0xc1100000 0x200000>;
31 reg = <0x4000 0x400>;
36 reg = <0x7c00 0x200>;
41 reg = <0x8100 0x8>;
46 reg = <0x84c0 0x18>;
53 reg = <0x84dc 0x18>;
60 reg = <0x8500 0x20>;
63 #size-cells = <0>;
69 reg = <0x8550 0x10>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dmeson-gx.dtsi64 hwrom_reserved: hwrom@0 {
65 reg = <0x0 0x0 0x0 0x1000000>;
71 reg = <0x0 0x10000000 0x0 0x200000>;
78 size = <0x0 0xbc00000>;
79 alignment = <0x0 0x400000>;
85 #address-cells = <0x2>;
86 #size-cells = <0x0>;
88 cpu0: cpu@0 {
91 reg = <0x0 0x0>;
94 clocks = <&scpi_dvfs 0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-gx.dtsi29 hwrom_reserved: hwrom@0 {
30 reg = <0x0 0x0 0x0 0x1000000>;
36 reg = <0x0 0x10000000 0x0 0x200000>;
42 reg = <0x0 0x05000000 0x0 0x300000>;
48 reg = <0x0 0x05300000 0x0 0x2000000>;
55 size = <0x0 0x10000000>;
56 alignment = <0x0 0x400000>;
84 #address-cells = <0x2>;
85 #size-cells = <0x0>;
87 cpu0: cpu@0 {
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_hwimg_nctl_raw_data_8852b.h30 0x8000, 0x00000008,
31 0x8008, 0x00000000,
32 0x8004, 0xf0862966,
33 0x800c, 0x78000000,
34 0x8010, 0x88015000,
35 0x8014, 0x80010100,
36 0x8018, 0x10010100,
37 0x801c, 0xa210bc00,
38 0x8020, 0x000403e0,
39 0x8024, 0x00072160,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_hwimg_nctl_raw_data_8852b.h30 0x8000, 0x00000008,
31 0x8008, 0x00000000,
32 0x8004, 0xf0862966,
33 0x800c, 0x78000000,
34 0x8010, 0x88015000,
35 0x8014, 0x80010100,
36 0x8018, 0x10010100,
37 0x801c, 0xa210bc00,
38 0x8020, 0x000403e0,
39 0x8024, 0x00072160,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]
H A Dcikd.h27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
34 #define DIDT_SQ_CTRL0 0x0
35 # define DIDT_CTRL_EN (1 << 0)
36 #define DIDT_DB_CTRL0 0x20
37 #define DIDT_TD_CTRL0 0x40
38 #define DIDT_TCP_CTRL0 0x60
41 #define DPM_TABLE_475 0x3F768
42 # define SamuBootLevel(x) ((x) << 0)
43 # define SamuBootLevel_MASK 0x000000ff
[all …]
H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]

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