Lines Matching +full:0 +full:x8680
64 hwrom_reserved: hwrom@0 {
65 reg = <0x0 0x0 0x0 0x1000000>;
71 reg = <0x0 0x10000000 0x0 0x200000>;
78 size = <0x0 0xbc00000>;
79 alignment = <0x0 0x400000>;
85 #address-cells = <0x2>;
86 #size-cells = <0x0>;
88 cpu0: cpu@0 {
91 reg = <0x0 0x0>;
94 clocks = <&scpi_dvfs 0>;
100 reg = <0x0 0x1>;
103 clocks = <&scpi_dvfs 0>;
109 reg = <0x0 0x2>;
112 clocks = <&scpi_dvfs 0>;
118 reg = <0x0 0x3>;
121 clocks = <&scpi_dvfs 0>;
146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
152 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
159 #clock-cells = <0>;
174 reg = <0x14 0x10>;
178 reg = <0x34 0x10>;
182 reg = <0x46 0x30>;
194 scpi_dvfs: scpi_clocks@0 {
197 clock-indices = <0>;
216 reg = <0x0 0xc1100000 0x0 0x100000>;
219 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
223 reg = <0x0 0x04404 0x0 0x20>;
229 reg = <0x0 0x84c0 0x0 0x14>;
237 reg = <0x0 0x84dc 0x0 0x14>;
245 reg = <0x0 0x08500 0x0 0x20>;
248 #size-cells = <0>;
254 reg = <0x0 0x08550 0x0 0x10>;
261 reg = <0x0 0x08650 0x0 0x10>;
268 reg = <0x0 0x8680 0x0 0x34>;
276 reg = <0x0 0x086c0 0x0 0x10>;
283 reg = <0x0 0x8700 0x0 0x14>;
291 reg = <0x0 0x087c0 0x0 0x20>;
294 #size-cells = <0>;
300 reg = <0x0 0x087e0 0x0 0x20>;
303 #size-cells = <0>;
309 reg = <0x0 0x08c80 0x0 0x80>;
311 #size-cells = <0>;
317 reg = <0x0 0x098d0 0x0 0x10>;
324 reg = <0x0 0xc4301000 0 0x1000>,
325 <0x0 0xc4302000 0 0x2000>,
326 <0x0 0xc4304000 0 0x2000>,
327 <0x0 0xc4306000 0 0x2000>;
332 #address-cells = <0>;
337 reg = <0x0 0xc8000000 0x0 0x14000>;
341 ranges = <0 0x0 0xc8000000 0x14000>;
343 cpu_scp_lpri: scp-shmem@0 {
345 reg = <0x13000 0x400>;
350 reg = <0x13400 0x400>;
356 reg = <0x0 0xc8100000 0x0 0x100000>;
359 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
363 reg = <0x0 0x00040 0x0 0x4>;
370 reg = <0x0 0x004c0 0x0 0x14>;
378 reg = <0x0 0x004e0 0x0 0x14>;
386 reg = <0x0 0x500 0x0 0x20>;
389 #size-cells = <0>;
395 reg = <0x0 0x00550 0x0 0x10>;
402 reg = <0x0 0x00580 0x0 0x40>;
410 reg = <0x0 0xc8834000 0x0 0x2000>;
413 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
417 reg = <0x0 0x0 0x0 0x4>;
423 reg = <0x0 0xc883c000 0x0 0x2000>;
426 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
430 reg = <0 0x404 0 0x4c>;
431 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
432 <0 209 IRQ_TYPE_EDGE_RISING>,
433 <0 210 IRQ_TYPE_EDGE_RISING>;
440 reg = <0x0 0xc9410000 0x0 0x10000
441 0x0 0xc8834540 0x0 0x4>;
442 interrupts = <0 8 1>;
449 reg = <0x0 0xd0000000 0x0 0x200000>;
452 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
456 reg = <0x0 0x70000 0x0 0x2000>;
463 reg = <0x0 0x72000 0x0 0x2000>;
470 reg = <0x0 0x74000 0x0 0x2000>;
478 reg = <0x0 0xd0100000 0x0 0x100000>,
479 <0x0 0xc883c000 0x0 0x1000>,
480 <0x0 0xc8838000 0x0 0x1000>;
484 #size-cells = <0>;
487 cvbs_vdac_port: port@0 {
488 reg = <0>;
503 reg = <0x0 0xc883a000 0x0 0x1c>;
506 #size-cells = <0>;
510 hdmi_tx_venc_port: port@0 {
511 reg = <0>;