1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dingxian Wen <shawn.wen@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _LT6911UXC_H_ 9*4882a593Smuzhiyun #define _LT6911UXC_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define LT6911UXC_FW_VERSION 0x2005 12*4882a593Smuzhiyun #define LT6911UXC_CHIPID 0x0417 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define I2C_ENABLE 0x1 15*4882a593Smuzhiyun #define I2C_DISABLE 0x0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AD_LMTX_WRITE_CLK 0x1b 18*4882a593Smuzhiyun #define RECEIVED_INT 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun // -------------- regs --------------- 21*4882a593Smuzhiyun #define I2C_EN_REG 0x80EE 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CHIPID_H 0x8101 24*4882a593Smuzhiyun #define CHIPID_L 0x8100 25*4882a593Smuzhiyun #define FW_VER_A 0x86a7 26*4882a593Smuzhiyun #define FW_VER_B 0x86a8 27*4882a593Smuzhiyun #define FW_VER_C 0x86a9 28*4882a593Smuzhiyun #define FW_VER_D 0x86aa 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HTOTAL_H 0x867c 31*4882a593Smuzhiyun #define HTOTAL_L 0x867d 32*4882a593Smuzhiyun #define HACT_H 0x8680 33*4882a593Smuzhiyun #define HACT_L 0x8681 34*4882a593Smuzhiyun #define VTOTAL_H 0x867a 35*4882a593Smuzhiyun #define VTOTAL_L 0x867b 36*4882a593Smuzhiyun #define VACT_H 0x867e 37*4882a593Smuzhiyun #define VACT_L 0x867f 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define HFP_H 0x8678 40*4882a593Smuzhiyun #define HFP_L 0x8679 41*4882a593Smuzhiyun #define HS_H 0x8672 42*4882a593Smuzhiyun #define HS_L 0x8673 43*4882a593Smuzhiyun #define HBP_H 0x8676 44*4882a593Smuzhiyun #define HBP_L 0x8677 45*4882a593Smuzhiyun #define VBP 0x8674 46*4882a593Smuzhiyun #define VFP 0x8675 47*4882a593Smuzhiyun #define VS 0x8671 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define HDMI_VERSION 0xb0a2 50*4882a593Smuzhiyun #define TMDS_CLK_H 0x8750 51*4882a593Smuzhiyun #define TMDS_CLK_M 0x8751 52*4882a593Smuzhiyun #define TMDS_CLK_L 0x8752 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define MIPI_LANES 0x86a2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define FM1_DET_CLK_SRC_SEL 0x8540 57*4882a593Smuzhiyun #define FREQ_METER_H 0x8548 58*4882a593Smuzhiyun #define FREQ_METER_M 0x8549 59*4882a593Smuzhiyun #define FREQ_METER_L 0x854a 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define INT_COMPARE_REG 0x86a6 62*4882a593Smuzhiyun #define INT_STATUS_86A3 0x86a3 63*4882a593Smuzhiyun #define INT_STATUS_86A5 0x86a5 64*4882a593Smuzhiyun #define AUDIO_IN_STATUS 0xb081 65*4882a593Smuzhiyun #define AUDIO_SAMPLE_RATAE_H 0xb0aa 66*4882a593Smuzhiyun #define AUDIO_SAMPLE_RATAE_L 0xb0ab 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69