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/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/
H A Dbnx2_fw.h17 .state_value_clear = 0xffffff,
24 .mips_view_base = 0x8000000,
33 .state_value_clear = 0xffffff,
40 .mips_view_base = 0x8000000,
49 .state_value_clear = 0xffffff,
56 .mips_view_base = 0x8000000,
65 .state_value_clear = 0xffffff,
72 .mips_view_base = 0x8000000,
81 .state_value_clear = 0xffffff,
88 .mips_view_base = 0x8000000,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dflctl-nand.txt26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx35-pdk.dts15 reg = <0x80000000 0x8000000>,
16 <0x90000000 0x8000000>;
22 pinctrl-0 = <&pinctrl_esdhc1>;
30 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
31 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
32 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
33 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
34 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
35 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
41 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
[all …]
H A Ds3c6410-smdk6410.dts24 reg = <0x50000000 0x8000000>;
31 fin_pll: oscillator-0 {
35 #clock-cells = <0>;
42 #clock-cells = <0>;
49 reg = <0x18000000 0x8000000>;
54 reg = <0x18000000 0x10000>;
70 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
77 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
83 pinctrl-0 = <&uart1_data>;
89 pinctrl-0 = <&uart2_data>;
[all …]
H A Darmada-xp-openblocks-ax3-4.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000
32 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
34 MBUS_ID(0x0c, 0x04) 0 0 0xd1200000 0x100000>;
44 devbus,badr-skew-ps = <0>;
47 devbus,rd-setup-ps = <0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dxilinx_zynqmp.h20 #define GICD_BASE 0xF9010000
21 #define GICC_BASE 0xF9020000
24 #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
29 #define CONFIG_SYS_MEMTEST_START 0
40 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
47 #define CONFIG_CONS_INDEX 0
84 #define CONFIG_SYS_LOAD_ADDR 0x8000000
87 #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
96 "system.dtb ram $fdt_addr $fdt_size\0" \
97 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
[all …]
H A Dti_armv7_omap.h21 * access CS0 at is 0x8000000.
25 #define CONFIG_SYS_NAND_BASE 0x8000000
H A Dti816x_evm.h16 #define CONFIG_ENV_SIZE 0x2000
21 "mtdids=" MTDIDS_DEFAULT "\0" \
22 "mtdparts=" MTDPARTS_DEFAULT "\0" \
26 "fatload mmc 0 ${loadaddr} uImage;" \
36 #define CONFIG_SYS_SDRAM_BASE 0x80000000
42 #define CONFIG_SYS_TIMERBASE 0x4802E000
51 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
63 * access CS0 at is 0x8000000.
65 #define CONFIG_SYS_NAND_BASE 0x8000000
91 #define MTDIDS_DEFAULT "nand0=nand.0"
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/doc/ld.html/
H A DSimple-Example.html88 0x10000, and that the data should start at address 0x8000000. Here is a
93 . = 0x10000;
95 . = 0x8000000;
111 &lsquo;<samp>SECTIONS</samp>&rsquo; command, the location counter has the value &lsquo;<samp>0</sam…
120 <p>Since the location counter is &lsquo;<samp>0x10000</samp>&rsquo; when the output section
122 &lsquo;<samp>.text</samp>&rsquo; section in the output file to be &lsquo;<samp>0x10000</samp>&rsquo…
126 at address &lsquo;<samp>0x8000000</samp>&rsquo;. After the linker places the &lsquo;<samp>.data</s…
128 &lsquo;<samp>0x8000000</samp>&rsquo; plus the size of the &lsquo;<samp>.data</samp>&rsquo; output s…
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/doc/ld.html/
H A DSimple-Example.html88 0x10000, and that the data should start at address 0x8000000. Here is a
93 . = 0x10000;
95 . = 0x8000000;
111 &lsquo;<samp>SECTIONS</samp>&rsquo; command, the location counter has the value &lsquo;<samp>0</sam…
120 <p>Since the location counter is &lsquo;<samp>0x10000</samp>&rsquo; when the output section
122 &lsquo;<samp>.text</samp>&rsquo; section in the output file to be &lsquo;<samp>0x10000</samp>&rsquo…
126 at address &lsquo;<samp>0x8000000</samp>&rsquo;. After the linker places the &lsquo;<samp>.data</s…
128 &lsquo;<samp>0x8000000</samp>&rsquo; plus the size of the &lsquo;<samp>.data</samp>&rsquo; output s…
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drcar-pci-ep.yaml72 reg = <0xfe000000 0x80000>,
73 <0xfe100000 0x100000>,
74 <0xfe200000 0x200000>,
75 <0x30000000 0x8000000>,
76 <0x38000000 0x8000000>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h13 { "pbl", 0x0, 0x80000000 }, /* PBL */
14 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
15 { "qdma", 0x0, 0x800000 }, /* qDMA */
16 { "edma", 0x0, 0x400000 }, /* eDMA */
17 { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
18 { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
19 { "sata", 0x0, 0x8000 }, /* SATA */
20 { "sec", 0x0, 0x200 }, /* SEC */
21 { "dcu", 0x0, 0x2 }, /* Display controller Unit */
22 { "qe", 0x0, 0x1 }, /* QUICC Engine */
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
45 reg = <0x101000 0x1000>;
50 reg = <0x102000 0x1000>;
55 reg = <0x103000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
/OK3568_Linux_fs/kernel/lib/
H A Dtest_min_heap.c37 int err = 0; in pop_verify_heap()
40 last = values[0]; in pop_verify_heap()
42 while (heap->nr > 0) { in pop_verify_heap()
44 if (last > values[0]) { in pop_verify_heap()
46 values[0]); in pop_verify_heap()
50 if (last < values[0]) { in pop_verify_heap()
52 values[0]); in pop_verify_heap()
56 last = values[0]; in pop_verify_heap()
64 int values[] = { 3, 1, 2, 4, 0x8000000, 0x7FFFFFF, 0, in test_heapify_all()
65 -3, -1, -2, -4, 0x8000000, 0x7FFFFFF }; in test_heapify_all()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h41 #define REG_PM_CTRLSTAT 0x44
43 #define REG_PCIE_CAP_LIST 0x58
45 #define REG_DEVICE_CAP 0x5C
46 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
47 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
49 #define REG_DEVICE_CTRL 0x60
50 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
52 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55 #define REG_VPD_CAP 0x6C
56 #define VPD_CAP_ID_MASK 0xff
[all …]

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