1*4882a593SmuzhiyunFLCTL NAND controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "renesas,shmobile-flctl-sh7372" 5*4882a593Smuzhiyun- reg : Address range of the FLCTL 6*4882a593Smuzhiyun- interrupts : flste IRQ number 7*4882a593Smuzhiyun- nand-bus-width : bus width to NAND chip 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun- dmas: DMA specifier(s) 11*4882a593Smuzhiyun- dma-names: name for each DMA specifier. Valid names are 12*4882a593Smuzhiyun "data_tx", "data_rx", "ecc_tx", "ecc_rx" 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe DMA fields are not used yet in the driver but are listed here for 15*4882a593Smuzhiyuncompleting the bindings. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe device tree may optionally contain sub-nodes describing partitions of the 18*4882a593Smuzhiyunaddress space. See partition.txt for more detail. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun flctl@e6a30000 { 23*4882a593Smuzhiyun #address-cells = <1>; 24*4882a593Smuzhiyun #size-cells = <1>; 25*4882a593Smuzhiyun compatible = "renesas,shmobile-flctl-sh7372"; 26*4882a593Smuzhiyun reg = <0xe6a30000 0x100>; 27*4882a593Smuzhiyun interrupts = <0x0d80>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun nand-bus-width = <16>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun dmas = <&dmac 1 /* data_tx */ 32*4882a593Smuzhiyun &dmac 2;> /* data_rx */ 33*4882a593Smuzhiyun dma-names = "data_tx", "data_rx"; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun system@0 { 36*4882a593Smuzhiyun label = "system"; 37*4882a593Smuzhiyun reg = <0x0 0x8000000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun userdata@8000000 { 41*4882a593Smuzhiyun label = "userdata"; 42*4882a593Smuzhiyun reg = <0x8000000 0x10000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun cache@18000000 { 46*4882a593Smuzhiyun label = "cache"; 47*4882a593Smuzhiyun reg = <0x18000000 0x8000000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50