1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for OpenBlocks AX3-4 board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 12*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 13*4882a593Smuzhiyun#include "armada-xp-mv78260.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "PlatHome OpenBlocks AX3-4 board"; 17*4882a593Smuzhiyun compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory@0 { 24*4882a593Smuzhiyun device_type = "memory"; 25*4882a593Smuzhiyun reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun soc { 29*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 30*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 31*4882a593Smuzhiyun MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000 32*4882a593Smuzhiyun MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 33*4882a593Smuzhiyun MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 34*4882a593Smuzhiyun MBUS_ID(0x0c, 0x04) 0 0 0xd1200000 0x100000>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun devbus-bootcs { 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Device Bus parameters are required */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Read parameters */ 42*4882a593Smuzhiyun devbus,bus-width = <16>; 43*4882a593Smuzhiyun devbus,turn-off-ps = <60000>; 44*4882a593Smuzhiyun devbus,badr-skew-ps = <0>; 45*4882a593Smuzhiyun devbus,acc-first-ps = <124000>; 46*4882a593Smuzhiyun devbus,acc-next-ps = <248000>; 47*4882a593Smuzhiyun devbus,rd-setup-ps = <0>; 48*4882a593Smuzhiyun devbus,rd-hold-ps = <0>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Write parameters */ 51*4882a593Smuzhiyun devbus,sync-enable = <0>; 52*4882a593Smuzhiyun devbus,wr-high-ps = <60000>; 53*4882a593Smuzhiyun devbus,wr-low-ps = <60000>; 54*4882a593Smuzhiyun devbus,ale-wr-ps = <60000>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* NOR 128 MiB */ 57*4882a593Smuzhiyun nor@0 { 58*4882a593Smuzhiyun compatible = "cfi-flash"; 59*4882a593Smuzhiyun reg = <0 0x8000000>; 60*4882a593Smuzhiyun bank-width = <2>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun internal-regs { 65*4882a593Smuzhiyun rtc@10300 { 66*4882a593Smuzhiyun /* No crystal connected to the internal RTC */ 67*4882a593Smuzhiyun status = "disabled"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun serial@12000 { 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun serial@12100 { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun leds { 77*4882a593Smuzhiyun compatible = "gpio-leds"; 78*4882a593Smuzhiyun pinctrl-names = "default"; 79*4882a593Smuzhiyun pinctrl-0 = <&led_pins>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun red_led { 82*4882a593Smuzhiyun label = "red_led"; 83*4882a593Smuzhiyun gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 84*4882a593Smuzhiyun default-state = "off"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun yellow_led { 88*4882a593Smuzhiyun label = "yellow_led"; 89*4882a593Smuzhiyun gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 90*4882a593Smuzhiyun default-state = "off"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun green_led { 94*4882a593Smuzhiyun label = "green_led"; 95*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; 96*4882a593Smuzhiyun default-state = "keep"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun gpio_keys { 101*4882a593Smuzhiyun compatible = "gpio-keys"; 102*4882a593Smuzhiyun #address-cells = <1>; 103*4882a593Smuzhiyun #size-cells = <0>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun init { 106*4882a593Smuzhiyun label = "Init Button"; 107*4882a593Smuzhiyun linux,code = <KEY_POWER>; 108*4882a593Smuzhiyun gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun ethernet@70000 { 113*4882a593Smuzhiyun status = "okay"; 114*4882a593Smuzhiyun phy = <&phy0>; 115*4882a593Smuzhiyun phy-mode = "sgmii"; 116*4882a593Smuzhiyun buffer-manager = <&bm>; 117*4882a593Smuzhiyun bm,pool-long = <0>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun ethernet@74000 { 120*4882a593Smuzhiyun status = "okay"; 121*4882a593Smuzhiyun phy = <&phy1>; 122*4882a593Smuzhiyun phy-mode = "sgmii"; 123*4882a593Smuzhiyun buffer-manager = <&bm>; 124*4882a593Smuzhiyun bm,pool-long = <1>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun ethernet@30000 { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun phy = <&phy2>; 129*4882a593Smuzhiyun phy-mode = "sgmii"; 130*4882a593Smuzhiyun buffer-manager = <&bm>; 131*4882a593Smuzhiyun bm,pool-long = <2>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun ethernet@34000 { 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun phy = <&phy3>; 136*4882a593Smuzhiyun phy-mode = "sgmii"; 137*4882a593Smuzhiyun buffer-manager = <&bm>; 138*4882a593Smuzhiyun bm,pool-long = <3>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun i2c@11000 { 141*4882a593Smuzhiyun status = "okay"; 142*4882a593Smuzhiyun clock-frequency = <400000>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun i2c@11100 { 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun clock-frequency = <400000>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun s35390a: s35390a@30 { 149*4882a593Smuzhiyun compatible = "s35390a"; 150*4882a593Smuzhiyun reg = <0x30>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun sata@a0000 { 154*4882a593Smuzhiyun nr-ports = <2>; 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Front side USB 0 */ 159*4882a593Smuzhiyun usb@50000 { 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Front side USB 1 */ 164*4882a593Smuzhiyun usb@51000 { 165*4882a593Smuzhiyun status = "okay"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun bm@c0000 { 169*4882a593Smuzhiyun status = "okay"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun bm-bppi { 174*4882a593Smuzhiyun status = "okay"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&pciec { 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun /* Internal mini-PCIe connector */ 182*4882a593Smuzhiyun pcie@1,0 { 183*4882a593Smuzhiyun /* Port 0, Lane 0 */ 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&mdio { 189*4882a593Smuzhiyun phy0: ethernet-phy@0 { 190*4882a593Smuzhiyun reg = <0>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun phy1: ethernet-phy@1 { 194*4882a593Smuzhiyun reg = <1>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun phy2: ethernet-phy@2 { 198*4882a593Smuzhiyun reg = <2>; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun phy3: ethernet-phy@3 { 202*4882a593Smuzhiyun reg = <3>; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun}; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun&pinctrl { 207*4882a593Smuzhiyun led_pins: led-pins-0 { 208*4882a593Smuzhiyun marvell,pins = "mpp49", "mpp51", "mpp53"; 209*4882a593Smuzhiyun marvell,function = "gpio"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun}; 212