1*4882a593Smuzhiyun /* bnx2_fw.h: QLogic bnx2 network driver. 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation 4*4882a593Smuzhiyun * Copyright (c) 2014-2015 QLogic Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 8*4882a593Smuzhiyun * the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Initialized Values for the Completion Processor. */ 12*4882a593Smuzhiyun static const struct cpu_reg cpu_reg_com = { 13*4882a593Smuzhiyun .mode = BNX2_COM_CPU_MODE, 14*4882a593Smuzhiyun .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT, 15*4882a593Smuzhiyun .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA, 16*4882a593Smuzhiyun .state = BNX2_COM_CPU_STATE, 17*4882a593Smuzhiyun .state_value_clear = 0xffffff, 18*4882a593Smuzhiyun .gpr0 = BNX2_COM_CPU_REG_FILE, 19*4882a593Smuzhiyun .evmask = BNX2_COM_CPU_EVENT_MASK, 20*4882a593Smuzhiyun .pc = BNX2_COM_CPU_PROGRAM_COUNTER, 21*4882a593Smuzhiyun .inst = BNX2_COM_CPU_INSTRUCTION, 22*4882a593Smuzhiyun .bp = BNX2_COM_CPU_HW_BREAKPOINT, 23*4882a593Smuzhiyun .spad_base = BNX2_COM_SCRATCH, 24*4882a593Smuzhiyun .mips_view_base = 0x8000000, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Initialized Values the Command Processor. */ 28*4882a593Smuzhiyun static const struct cpu_reg cpu_reg_cp = { 29*4882a593Smuzhiyun .mode = BNX2_CP_CPU_MODE, 30*4882a593Smuzhiyun .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT, 31*4882a593Smuzhiyun .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA, 32*4882a593Smuzhiyun .state = BNX2_CP_CPU_STATE, 33*4882a593Smuzhiyun .state_value_clear = 0xffffff, 34*4882a593Smuzhiyun .gpr0 = BNX2_CP_CPU_REG_FILE, 35*4882a593Smuzhiyun .evmask = BNX2_CP_CPU_EVENT_MASK, 36*4882a593Smuzhiyun .pc = BNX2_CP_CPU_PROGRAM_COUNTER, 37*4882a593Smuzhiyun .inst = BNX2_CP_CPU_INSTRUCTION, 38*4882a593Smuzhiyun .bp = BNX2_CP_CPU_HW_BREAKPOINT, 39*4882a593Smuzhiyun .spad_base = BNX2_CP_SCRATCH, 40*4882a593Smuzhiyun .mips_view_base = 0x8000000, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Initialized Values for the RX Processor. */ 44*4882a593Smuzhiyun static const struct cpu_reg cpu_reg_rxp = { 45*4882a593Smuzhiyun .mode = BNX2_RXP_CPU_MODE, 46*4882a593Smuzhiyun .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT, 47*4882a593Smuzhiyun .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA, 48*4882a593Smuzhiyun .state = BNX2_RXP_CPU_STATE, 49*4882a593Smuzhiyun .state_value_clear = 0xffffff, 50*4882a593Smuzhiyun .gpr0 = BNX2_RXP_CPU_REG_FILE, 51*4882a593Smuzhiyun .evmask = BNX2_RXP_CPU_EVENT_MASK, 52*4882a593Smuzhiyun .pc = BNX2_RXP_CPU_PROGRAM_COUNTER, 53*4882a593Smuzhiyun .inst = BNX2_RXP_CPU_INSTRUCTION, 54*4882a593Smuzhiyun .bp = BNX2_RXP_CPU_HW_BREAKPOINT, 55*4882a593Smuzhiyun .spad_base = BNX2_RXP_SCRATCH, 56*4882a593Smuzhiyun .mips_view_base = 0x8000000, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Initialized Values for the TX Patch-up Processor. */ 60*4882a593Smuzhiyun static const struct cpu_reg cpu_reg_tpat = { 61*4882a593Smuzhiyun .mode = BNX2_TPAT_CPU_MODE, 62*4882a593Smuzhiyun .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT, 63*4882a593Smuzhiyun .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA, 64*4882a593Smuzhiyun .state = BNX2_TPAT_CPU_STATE, 65*4882a593Smuzhiyun .state_value_clear = 0xffffff, 66*4882a593Smuzhiyun .gpr0 = BNX2_TPAT_CPU_REG_FILE, 67*4882a593Smuzhiyun .evmask = BNX2_TPAT_CPU_EVENT_MASK, 68*4882a593Smuzhiyun .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER, 69*4882a593Smuzhiyun .inst = BNX2_TPAT_CPU_INSTRUCTION, 70*4882a593Smuzhiyun .bp = BNX2_TPAT_CPU_HW_BREAKPOINT, 71*4882a593Smuzhiyun .spad_base = BNX2_TPAT_SCRATCH, 72*4882a593Smuzhiyun .mips_view_base = 0x8000000, 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Initialized Values for the TX Processor. */ 76*4882a593Smuzhiyun static const struct cpu_reg cpu_reg_txp = { 77*4882a593Smuzhiyun .mode = BNX2_TXP_CPU_MODE, 78*4882a593Smuzhiyun .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT, 79*4882a593Smuzhiyun .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA, 80*4882a593Smuzhiyun .state = BNX2_TXP_CPU_STATE, 81*4882a593Smuzhiyun .state_value_clear = 0xffffff, 82*4882a593Smuzhiyun .gpr0 = BNX2_TXP_CPU_REG_FILE, 83*4882a593Smuzhiyun .evmask = BNX2_TXP_CPU_EVENT_MASK, 84*4882a593Smuzhiyun .pc = BNX2_TXP_CPU_PROGRAM_COUNTER, 85*4882a593Smuzhiyun .inst = BNX2_TXP_CPU_INSTRUCTION, 86*4882a593Smuzhiyun .bp = BNX2_TXP_CPU_HW_BREAKPOINT, 87*4882a593Smuzhiyun .spad_base = BNX2_TXP_SCRATCH, 88*4882a593Smuzhiyun .mips_view_base = 0x8000000, 89*4882a593Smuzhiyun }; 90