1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ti_armv7_omap.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The various ARMv7 SoCs from TI all share a number of IP blocks when 9*4882a593Smuzhiyun * implementing a given feature. This is meant to isolate the features 10*4882a593Smuzhiyun * that are based on OMAP architecture. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef __CONFIG_TI_ARMV7_OMAP_H__ 13*4882a593Smuzhiyun #define __CONFIG_TI_ARMV7_OMAP_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* I2C IP block */ 16*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 17*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * GPMC NAND block. We support 1 device and the physical address to 21*4882a593Smuzhiyun * access CS0 at is 0x8000000. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifdef CONFIG_NAND 24*4882a593Smuzhiyun #ifndef CONFIG_SYS_NAND_BASE 25*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x8000000 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Now for the remaining common defines */ 31*4882a593Smuzhiyun #include <configs/ti_armv7_common.h> 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ 34