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/OK3568_Linux_fs/kernel/drivers/phy/ti/
H A Dphy-gmii-sel.c21 #define AM33XX_GMII_SEL_MODE_MII 0
26 PHY_GMII_SEL_PORT_MODE = 0,
64 int ret, rgmii_id = 0; in phy_gmii_sel_mode()
65 u32 gmii_sel_mode = 0; in phy_gmii_sel_mode()
125 return 0; in phy_gmii_sel_mode()
131 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
132 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
133 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
136 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
137 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dmc.h15 u32 reserved0[4]; /* offset 0x00 - 0x0C */
16 u32 mc_smmu_config; /* offset 0x10 */
17 u32 mc_smmu_tlb_config; /* offset 0x14 */
18 u32 mc_smmu_ptc_config; /* offset 0x18 */
19 u32 mc_smmu_ptb_asid; /* offset 0x1C */
20 u32 mc_smmu_ptb_data; /* offset 0x20 */
21 u32 reserved1[3]; /* offset 0x24 - 0x2C */
22 u32 mc_smmu_tlb_flush; /* offset 0x30 */
23 u32 mc_smmu_ptc_flush; /* offset 0x34 */
24 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dmc.h15 u32 reserved0[4]; /* offset 0x00 - 0x0C */
16 u32 mc_smmu_config; /* offset 0x10 */
17 u32 mc_smmu_tlb_config; /* offset 0x14 */
18 u32 mc_smmu_ptc_config; /* offset 0x18 */
19 u32 mc_smmu_ptb_asid; /* offset 0x1C */
20 u32 mc_smmu_ptb_data; /* offset 0x20 */
21 u32 reserved1[3]; /* offset 0x24 - 0x2C */
22 u32 mc_smmu_tlb_flush; /* offset 0x30 */
23 u32 mc_smmu_ptc_flush; /* offset 0x34 */
24 u32 mc_smmu_asid_security; /* offset 0x38 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra72x-mmc-iodelay.dtsi45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Ddra74x-mmc-iodelay.dtsi43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
47 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
48 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
54 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
55 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
56 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
57 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/kernel/tools/perf/tests/
H A Dmem2node.c17 { .node = 0, .map = "0" },
33 for (i = 0; i < map->nr; i++) { in get_bitmap()
51 .memory_nodes = (struct memory_node *) &nodes[0], in test__mem2node()
53 .memory_bsize = 0x100, in test__mem2node()
57 for (i = 0; i < ARRAY_SIZE(nodes); i++) { in test__mem2node()
66 T("failed: mem2node__node", 0 == mem2node__node(&map, 0x50)); in test__mem2node()
67 T("failed: mem2node__node", 1 == mem2node__node(&map, 0x100)); in test__mem2node()
68 T("failed: mem2node__node", 1 == mem2node__node(&map, 0x250)); in test__mem2node()
69 T("failed: mem2node__node", 3 == mem2node__node(&map, 0x500)); in test__mem2node()
70 T("failed: mem2node__node", 3 == mem2node__node(&map, 0x650)); in test__mem2node()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dmc.h14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
22 u32 mc_smmu_ptc_flush; /* offset 0x34 */
23 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dmc.h14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
22 u32 mc_smmu_ptc_flush; /* offset 0x34 */
23 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx53-pinfunc.h17 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
18 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
19 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
20 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
21 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
22 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
23 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
24 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
25 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
26 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-gmii-sel.yaml102 reg = <0x650 0x4>;
/OK3568_Linux_fs/kernel/drivers/nvmem/
H A Dvf610-ocotp.c23 #define OCOTP_CTRL_REG 0x00
24 #define OCOTP_CTRL_SET 0x04
25 #define OCOTP_CTRL_CLR 0x08
26 #define OCOTP_TIMING 0x10
27 #define OCOTP_DATA 0x20
28 #define OCOTP_READ_CTRL_REG 0x30
29 #define OCOTP_READ_FUSE_DATA 0x40
33 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
35 #define OCOTP_CTRL_ADDR 0
36 #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h10 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
11 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054
14 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
15 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
16 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254
17 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
27 #define DEFAULT_PAUSE_TIME 0xFFFF
29 #define BGX_ID_MASK 0x3
30 #define LMAC_ID_MASK 0x3
35 #define BGX_CMRX_CFG 0x00
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/apple/
H A Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A D53c700.scr25 ABSOLUTE Device_ID = 0 ; ID of target for command
26 ABSOLUTE MessageCount = 0 ; Number of bytes in message
27 ABSOLUTE MessageLocation = 0 ; Addr of message
28 ABSOLUTE CommandCount = 0 ; Number of bytes in command
29 ABSOLUTE CommandAddress = 0 ; Addr of Command
30 ABSOLUTE StatusAddress = 0 ; Addr to receive status return
31 ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
39 ABSOLUTE SGScriptStartAddress = 0
42 ; this: 0xPRS where
45 ABSOLUTE AFTER_SELECTION = 0x100
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Ddenali.h16 #define DEVICE_RESET 0x0
19 #define TRANSFER_SPARE_REG 0x10
20 #define TRANSFER_SPARE_REG__FLAG BIT(0)
22 #define LOAD_WAIT_CNT 0x20
23 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
25 #define PROGRAM_WAIT_CNT 0x30
26 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
28 #define ERASE_WAIT_CNT 0x40
29 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
31 #define INT_MON_CYCCNT 0x50
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dw83627ehf.rst141 0 (stop) to 255 (full)
146 * 1 Manual mode, write to pwm file any value 0-255 (full speed)
166 * 0 DC output (0 - 12v)
176 (range 0 - 127000)
178 tolerance, unit millidegree Celsius (range 0 - 15000)
216 0x49 only on DHG, selects temperature source for AUX fan,
218 0x4a not completely documented for the EHF and the DHG
224 0x58 Chip ID: 0xa1=EHF 0xc1=DHG
225 0x5e only on DHG, has bits to enable "current mode"
228 0x45b only on EHF, bit 3, vin4 alarm (EHF supports 10
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Ddenali.h17 #define DEVICE_RESET 0x0
20 #define TRANSFER_SPARE_REG 0x10
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
23 #define LOAD_WAIT_CNT 0x20
24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT 0x30
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT 0x40
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT 0x50
[all …]

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