Lines Matching +full:0 +full:x650
16 #define DEVICE_RESET 0x0
19 #define TRANSFER_SPARE_REG 0x10
20 #define TRANSFER_SPARE_REG__FLAG BIT(0)
22 #define LOAD_WAIT_CNT 0x20
23 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
25 #define PROGRAM_WAIT_CNT 0x30
26 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
28 #define ERASE_WAIT_CNT 0x40
29 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
31 #define INT_MON_CYCCNT 0x50
32 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
34 #define RB_PIN_ENABLED 0x60
37 #define MULTIPLANE_OPERATION 0x70
38 #define MULTIPLANE_OPERATION__FLAG BIT(0)
40 #define MULTIPLANE_READ_ENABLE 0x80
41 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
43 #define COPYBACK_DISABLE 0x90
44 #define COPYBACK_DISABLE__FLAG BIT(0)
46 #define CACHE_WRITE_ENABLE 0xa0
47 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
49 #define CACHE_READ_ENABLE 0xb0
50 #define CACHE_READ_ENABLE__FLAG BIT(0)
52 #define PREFETCH_MODE 0xc0
53 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
56 #define CHIP_ENABLE_DONT_CARE 0xd0
57 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
59 #define ECC_ENABLE 0xe0
60 #define ECC_ENABLE__FLAG BIT(0)
62 #define GLOBAL_INT_ENABLE 0xf0
63 #define GLOBAL_INT_EN_FLAG BIT(0)
65 #define TWHR2_AND_WE_2_RE 0x100
66 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
69 #define TCWAW_AND_ADDR_2_DATA 0x110
71 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
74 #define RE_2_WE 0x120
75 #define RE_2_WE__VALUE GENMASK(5, 0)
77 #define ACC_CLKS 0x130
78 #define ACC_CLKS__VALUE GENMASK(3, 0)
80 #define NUMBER_OF_PLANES 0x140
81 #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
83 #define PAGES_PER_BLOCK 0x150
84 #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
86 #define DEVICE_WIDTH 0x160
87 #define DEVICE_WIDTH__VALUE GENMASK(1, 0)
89 #define DEVICE_MAIN_AREA_SIZE 0x170
90 #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
92 #define DEVICE_SPARE_AREA_SIZE 0x180
93 #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
95 #define TWO_ROW_ADDR_CYCLES 0x190
96 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
98 #define MULTIPLANE_ADDR_RESTRICT 0x1a0
99 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
101 #define ECC_CORRECTION 0x1b0
102 #define ECC_CORRECTION__VALUE GENMASK(4, 0)
105 #define READ_MODE 0x1c0
106 #define READ_MODE__VALUE GENMASK(3, 0)
108 #define WRITE_MODE 0x1d0
109 #define WRITE_MODE__VALUE GENMASK(3, 0)
111 #define COPYBACK_MODE 0x1e0
112 #define COPYBACK_MODE__VALUE GENMASK(3, 0)
114 #define RDWR_EN_LO_CNT 0x1f0
115 #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
117 #define RDWR_EN_HI_CNT 0x200
118 #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
120 #define MAX_RD_DELAY 0x210
121 #define MAX_RD_DELAY__VALUE GENMASK(3, 0)
123 #define CS_SETUP_CNT 0x220
124 #define CS_SETUP_CNT__VALUE GENMASK(4, 0)
127 #define SPARE_AREA_SKIP_BYTES 0x230
128 #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
130 #define SPARE_AREA_MARKER 0x240
131 #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
133 #define DEVICES_CONNECTED 0x250
134 #define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
136 #define DIE_MASK 0x260
137 #define DIE_MASK__VALUE GENMASK(7, 0)
139 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
140 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
142 #define WRITE_PROTECT 0x280
143 #define WRITE_PROTECT__FLAG BIT(0)
145 #define RE_2_RE 0x290
146 #define RE_2_RE__VALUE GENMASK(5, 0)
148 #define MANUFACTURER_ID 0x300
149 #define MANUFACTURER_ID__VALUE GENMASK(7, 0)
151 #define DEVICE_ID 0x310
152 #define DEVICE_ID__VALUE GENMASK(7, 0)
154 #define DEVICE_PARAM_0 0x320
155 #define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
157 #define DEVICE_PARAM_1 0x330
158 #define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
160 #define DEVICE_PARAM_2 0x340
161 #define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
163 #define LOGICAL_PAGE_DATA_SIZE 0x350
164 #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
166 #define LOGICAL_PAGE_SPARE_SIZE 0x360
167 #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
169 #define REVISION 0x370
170 #define REVISION__VALUE GENMASK(15, 0)
172 #define ONFI_DEVICE_FEATURES 0x380
173 #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
175 #define ONFI_OPTIONAL_COMMANDS 0x390
176 #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
178 #define ONFI_TIMING_MODE 0x3a0
179 #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
181 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
182 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
184 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
185 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
188 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
189 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
191 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
192 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
194 #define FEATURES 0x3f0
195 #define FEATURES__N_BANKS GENMASK(1, 0)
204 #define TRANSFER_MODE 0x400
205 #define TRANSFER_MODE__VALUE GENMASK(1, 0)
207 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
208 #define INTR_EN(bank) (0x420 + (bank) * 0x50)
209 /* bit[1:0] is used differently depending on IP version */
210 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
211 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
229 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
230 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
231 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
233 #define ECC_THRESHOLD 0x600
234 #define ECC_THRESHOLD__VALUE GENMASK(9, 0)
236 #define ECC_ERROR_BLOCK_ADDRESS 0x610
237 #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
239 #define ECC_ERROR_PAGE_ADDRESS 0x620
240 #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
243 #define ECC_ERROR_ADDRESS 0x630
244 #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
247 #define ERR_CORRECTION_INFO 0x640
248 #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
253 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
255 #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
258 #define CFG_DATA_BLOCK_SIZE 0x6b0
260 #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
262 #define CFG_NUM_DATA_BLOCKS 0x6d0
264 #define CFG_META_DATA_SIZE 0x6e0
266 #define DMA_ENABLE 0x700
267 #define DMA_ENABLE__FLAG BIT(0)
269 #define IGNORE_ECC_DONE 0x710
270 #define IGNORE_ECC_DONE__FLAG BIT(0)
272 #define DMA_INTR 0x720
273 #define DMA_INTR_EN 0x730
274 #define DMA_INTR__TARGET_ERROR BIT(0)
281 #define TARGET_ERR_ADDR_LO 0x740
282 #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
284 #define TARGET_ERR_ADDR_HI 0x750
285 #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
287 #define CHNL_ACTIVE 0x760
288 #define CHNL_ACTIVE__CHANNEL0 BIT(0)
323 #define DENALI_CAP_HW_ECC_FIXUP BIT(0)