1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mace.h - definitions for the registers in the "Big Mac" 4*4882a593Smuzhiyun * Ethernet controller found in PowerMac G3 models. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1998 Randy Gobbel. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal" 10*4882a593Smuzhiyun * (HME) controller. See sunhme.h 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* register offsets */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* global status and control */ 17*4882a593Smuzhiyun #define XIFC 0x000 /* low-level interface control */ 18*4882a593Smuzhiyun # define TxOutputEnable 0x0001 /* output driver enable */ 19*4882a593Smuzhiyun # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */ 20*4882a593Smuzhiyun # define MIILoopback 0x0004 /* Loopback-mode MII enable */ 21*4882a593Smuzhiyun # define MIILoopbackBits 0x0006 22*4882a593Smuzhiyun # define MIIBuffDisable 0x0008 /* MII receive buffer disable */ 23*4882a593Smuzhiyun # define SQETestEnable 0x0010 /* SQE test enable */ 24*4882a593Smuzhiyun # define SQETimeWindow 0x03e0 /* SQE time window */ 25*4882a593Smuzhiyun # define XIFLanceMode 0x0010 /* Lance mode enable */ 26*4882a593Smuzhiyun # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */ 27*4882a593Smuzhiyun #define TXFIFOCSR 0x100 /* transmit FIFO control */ 28*4882a593Smuzhiyun # define TxFIFOEnable 0x0001 29*4882a593Smuzhiyun #define TXTH 0x110 /* transmit threshold */ 30*4882a593Smuzhiyun # define TxThreshold 0x0004 31*4882a593Smuzhiyun #define RXFIFOCSR 0x120 /* receive FIFO control */ 32*4882a593Smuzhiyun # define RxFIFOEnable 0x0001 33*4882a593Smuzhiyun #define MEMADD 0x130 /* memory address, unknown function */ 34*4882a593Smuzhiyun #define MEMDATAHI 0x140 /* memory data high, presently unused in driver */ 35*4882a593Smuzhiyun #define MEMDATALO 0x150 /* memory data low, presently unused in driver */ 36*4882a593Smuzhiyun #define XCVRIF 0x160 /* transceiver interface control */ 37*4882a593Smuzhiyun # define COLActiveLow 0x0002 38*4882a593Smuzhiyun # define SerialMode 0x0004 39*4882a593Smuzhiyun # define ClkBit 0x0008 40*4882a593Smuzhiyun # define LinkStatus 0x0100 41*4882a593Smuzhiyun #define CHIPID 0x170 /* chip ID */ 42*4882a593Smuzhiyun #define MIFCSR 0x180 /* ??? */ 43*4882a593Smuzhiyun #define SROMCSR 0x190 /* SROM control */ 44*4882a593Smuzhiyun # define ChipSelect 0x0001 45*4882a593Smuzhiyun # define Clk 0x0002 46*4882a593Smuzhiyun #define TXPNTR 0x1a0 /* transmit pointer */ 47*4882a593Smuzhiyun #define RXPNTR 0x1b0 /* receive pointer */ 48*4882a593Smuzhiyun #define STATUS 0x200 /* status--reading this clears it */ 49*4882a593Smuzhiyun #define INTDISABLE 0x210 /* interrupt enable/disable control */ 50*4882a593Smuzhiyun /* bits below are the same in both STATUS and INTDISABLE registers */ 51*4882a593Smuzhiyun # define FrameReceived 0x00000001 /* Received a frame */ 52*4882a593Smuzhiyun # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */ 53*4882a593Smuzhiyun # define RxAlignCntExp 0x00000004 /* Align-error counter expired */ 54*4882a593Smuzhiyun # define RxCRCCntExp 0x00000008 /* CRC-error counter expired */ 55*4882a593Smuzhiyun # define RxLenCntExp 0x00000010 /* Length-error counter expired */ 56*4882a593Smuzhiyun # define RxOverFlow 0x00000020 /* Receive FIFO overflow */ 57*4882a593Smuzhiyun # define RxCodeViolation 0x00000040 /* Code-violation counter expired */ 58*4882a593Smuzhiyun # define SQETestError 0x00000080 /* Test error in XIF for SQE */ 59*4882a593Smuzhiyun # define FrameSent 0x00000100 /* Transmitted a frame */ 60*4882a593Smuzhiyun # define TxUnderrun 0x00000200 /* Transmit FIFO underrun */ 61*4882a593Smuzhiyun # define TxMaxSizeError 0x00000400 /* Max-packet size error */ 62*4882a593Smuzhiyun # define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */ 63*4882a593Smuzhiyun # define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */ 64*4882a593Smuzhiyun # define TxLateCollExp 0x00002000 /* Late-collision counter expired */ 65*4882a593Smuzhiyun # define TxNetworkCollExp 0x00004000 /* First-collision counter expired */ 66*4882a593Smuzhiyun # define TxDeferTimerExp 0x00008000 /* Defer-timer expired */ 67*4882a593Smuzhiyun # define RxFIFOToHost 0x00010000 /* Data moved from FIFO to host */ 68*4882a593Smuzhiyun # define RxNoDescriptors 0x00020000 /* No more receive descriptors */ 69*4882a593Smuzhiyun # define RxDMAError 0x00040000 /* Error during receive DMA */ 70*4882a593Smuzhiyun # define RxDMALateErr 0x00080000 /* Receive DMA, data late */ 71*4882a593Smuzhiyun # define RxParityErr 0x00100000 /* Parity error during receive DMA */ 72*4882a593Smuzhiyun # define RxTagError 0x00200000 /* Tag error during receive DMA */ 73*4882a593Smuzhiyun # define TxEOPError 0x00400000 /* Tx descriptor did not have EOP set */ 74*4882a593Smuzhiyun # define MIFIntrEvent 0x00800000 /* MIF is signaling an interrupt */ 75*4882a593Smuzhiyun # define TxHostToFIFO 0x01000000 /* Data moved from host to FIFO */ 76*4882a593Smuzhiyun # define TxFIFOAllSent 0x02000000 /* Transmitted all packets in FIFO */ 77*4882a593Smuzhiyun # define TxDMAError 0x04000000 /* Error during transmit DMA */ 78*4882a593Smuzhiyun # define TxDMALateError 0x08000000 /* Late error during transmit DMA */ 79*4882a593Smuzhiyun # define TxParityError 0x10000000 /* Parity error during transmit DMA */ 80*4882a593Smuzhiyun # define TxTagError 0x20000000 /* Tag error during transmit DMA */ 81*4882a593Smuzhiyun # define PIOError 0x40000000 /* PIO access got an error */ 82*4882a593Smuzhiyun # define PIOParityError 0x80000000 /* PIO access got a parity error */ 83*4882a593Smuzhiyun # define DisableAll 0xffffffff 84*4882a593Smuzhiyun # define EnableAll 0x00000000 85*4882a593Smuzhiyun /* # define NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */ 86*4882a593Smuzhiyun # define EnableNormal ~(FrameReceived | FrameSent) 87*4882a593Smuzhiyun # define EnableErrors (FrameReceived | FrameSent) 88*4882a593Smuzhiyun # define RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \ 89*4882a593Smuzhiyun RxLenCntExp | RxOverFlow | RxCodeViolation) 90*4882a593Smuzhiyun # define TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \ 91*4882a593Smuzhiyun TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* transmit control */ 94*4882a593Smuzhiyun #define TXRST 0x420 /* transmit reset */ 95*4882a593Smuzhiyun # define TxResetBit 0x0001 96*4882a593Smuzhiyun #define TXCFG 0x430 /* transmit configuration control*/ 97*4882a593Smuzhiyun # define TxMACEnable 0x0001 /* output driver enable */ 98*4882a593Smuzhiyun # define TxSlowMode 0x0020 /* enable slow mode */ 99*4882a593Smuzhiyun # define TxIgnoreColl 0x0040 /* ignore transmit collisions */ 100*4882a593Smuzhiyun # define TxNoFCS 0x0080 /* do not emit FCS */ 101*4882a593Smuzhiyun # define TxNoBackoff 0x0100 /* no backoff in case of collisions */ 102*4882a593Smuzhiyun # define TxFullDuplex 0x0200 /* enable full-duplex */ 103*4882a593Smuzhiyun # define TxNeverGiveUp 0x0400 /* don't give up on transmits */ 104*4882a593Smuzhiyun #define IPG1 0x440 /* Inter-packet gap 1 */ 105*4882a593Smuzhiyun #define IPG2 0x450 /* Inter-packet gap 2 */ 106*4882a593Smuzhiyun #define ALIMIT 0x460 /* Transmit attempt limit */ 107*4882a593Smuzhiyun #define SLOT 0x470 /* Transmit slot time */ 108*4882a593Smuzhiyun #define PALEN 0x480 /* Size of transmit preamble */ 109*4882a593Smuzhiyun #define PAPAT 0x490 /* Pattern for transmit preamble */ 110*4882a593Smuzhiyun #define TXSFD 0x4a0 /* Transmit frame delimiter */ 111*4882a593Smuzhiyun #define JAM 0x4b0 /* Jam size */ 112*4882a593Smuzhiyun #define TXMAX 0x4c0 /* Transmit max pkt size */ 113*4882a593Smuzhiyun #define TXMIN 0x4d0 /* Transmit min pkt size */ 114*4882a593Smuzhiyun #define PAREG 0x4e0 /* Count of transmit peak attempts */ 115*4882a593Smuzhiyun #define DCNT 0x4f0 /* Transmit defer timer */ 116*4882a593Smuzhiyun #define NCCNT 0x500 /* Transmit normal-collision counter */ 117*4882a593Smuzhiyun #define NTCNT 0x510 /* Transmit first-collision counter */ 118*4882a593Smuzhiyun #define EXCNT 0x520 /* Transmit excess-collision counter */ 119*4882a593Smuzhiyun #define LTCNT 0x530 /* Transmit late-collision counter */ 120*4882a593Smuzhiyun #define RSEED 0x540 /* Transmit random number seed */ 121*4882a593Smuzhiyun #define TXSM 0x550 /* Transmit state machine */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* receive control */ 124*4882a593Smuzhiyun #define RXRST 0x620 /* receive reset */ 125*4882a593Smuzhiyun # define RxResetValue 0x0000 126*4882a593Smuzhiyun #define RXCFG 0x630 /* receive configuration control */ 127*4882a593Smuzhiyun # define RxMACEnable 0x0001 /* receiver overall enable */ 128*4882a593Smuzhiyun # define RxCFGReserved 0x0004 129*4882a593Smuzhiyun # define RxPadStripEnab 0x0020 /* enable pad byte stripping */ 130*4882a593Smuzhiyun # define RxPromiscEnable 0x0040 /* turn on promiscuous mode */ 131*4882a593Smuzhiyun # define RxNoErrCheck 0x0080 /* disable receive error checking */ 132*4882a593Smuzhiyun # define RxCRCNoStrip 0x0100 /* disable auto-CRC-stripping */ 133*4882a593Smuzhiyun # define RxRejectOwnPackets 0x0200 /* don't receive our own packets */ 134*4882a593Smuzhiyun # define RxGrpPromisck 0x0400 /* enable group promiscuous mode */ 135*4882a593Smuzhiyun # define RxHashFilterEnable 0x0800 /* enable hash filter */ 136*4882a593Smuzhiyun # define RxAddrFilterEnable 0x1000 /* enable address filter */ 137*4882a593Smuzhiyun #define RXMAX 0x640 /* Max receive packet size */ 138*4882a593Smuzhiyun #define RXMIN 0x650 /* Min receive packet size */ 139*4882a593Smuzhiyun #define MADD2 0x660 /* our enet address, high part */ 140*4882a593Smuzhiyun #define MADD1 0x670 /* our enet address, middle part */ 141*4882a593Smuzhiyun #define MADD0 0x680 /* our enet address, low part */ 142*4882a593Smuzhiyun #define FRCNT 0x690 /* receive frame counter */ 143*4882a593Smuzhiyun #define LECNT 0x6a0 /* Receive excess length error counter */ 144*4882a593Smuzhiyun #define AECNT 0x6b0 /* Receive misaligned error counter */ 145*4882a593Smuzhiyun #define FECNT 0x6c0 /* Receive CRC error counter */ 146*4882a593Smuzhiyun #define RXSM 0x6d0 /* Receive state machine */ 147*4882a593Smuzhiyun #define RXCV 0x6e0 /* Receive code violation */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define BHASH3 0x700 /* multicast hash register */ 150*4882a593Smuzhiyun #define BHASH2 0x710 /* multicast hash register */ 151*4882a593Smuzhiyun #define BHASH1 0x720 /* multicast hash register */ 152*4882a593Smuzhiyun #define BHASH0 0x730 /* multicast hash register */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define AFR2 0x740 /* address filtering setup? */ 155*4882a593Smuzhiyun #define AFR1 0x750 /* address filtering setup? */ 156*4882a593Smuzhiyun #define AFR0 0x760 /* address filtering setup? */ 157*4882a593Smuzhiyun #define AFCR 0x770 /* address filter compare register? */ 158*4882a593Smuzhiyun # define EnableAllCompares 0x0fff 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* bits in XIFC */ 161