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/OK3568_Linux_fs/kernel/scripts/
H A Dextract_xc3028.pl25 my $debug=0;
50 while ($length > 0) {
66 my $msb = ($val >> 8) &0xff;
67 my $lsb = $val & 0xff;
75 my $l3 = ($val >> 24) & 0xff;
76 my $l2 = ($val >> 16) & 0xff;
77 my $l1 = ($val >> 8) & 0xff;
78 my $l0 = $val & 0xff;
87 my $l7 = ($msb_val >> 24) & 0xff;
88 my $l6 = ($msb_val >> 16) & 0xff;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/lib/
H A Dfeature-fixups.c67 return 0; in patch_alt_instruction()
83 return 0; in patch_feature_section()
98 return 0; in patch_feature_section()
131 instrs[0] = 0x60000000; /* nop */ in do_stf_entry_barrier_fixups()
132 instrs[1] = 0x60000000; /* nop */ in do_stf_entry_barrier_fixups()
133 instrs[2] = 0x60000000; /* nop */ in do_stf_entry_barrier_fixups()
135 i = 0; in do_stf_entry_barrier_fixups()
137 instrs[i++] = 0x7d4802a6; /* mflr r10 */ in do_stf_entry_barrier_fixups()
138 instrs[i++] = 0x60000000; /* branch patched below */ in do_stf_entry_barrier_fixups()
139 instrs[i++] = 0x7d4803a6; /* mtlr r10 */ in do_stf_entry_barrier_fixups()
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Drk3036_common.h21 #define CONFIG_SYS_TEXT_BASE 0x60200000
22 #define CONFIG_SYS_INIT_SP_ADDR 0x60400000
23 #define CONFIG_SYS_LOAD_ADDR 0x61800800
24 #define CONFIG_SPL_TEXT_BASE 0x60000000
26 #define CONFIG_TPL_STACK 0x10081fff
27 #define CONFIG_TPL_TEXT_BASE 0x10081000
31 #define CONFIG_ROCKUSB_G_DNL_PID 0x301A
36 #define CONFIG_SYS_SDRAM_BASE 0x60000000
38 #define SDRAM_MAX_SIZE 0x80000000
51 "scriptaddr1=0x60000000\0" \
[all …]
H A Drk3188_common.h24 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
25 #define CONFIG_SYS_TEXT_BASE 0x60000000
27 #define CONFIG_SYS_TEXT_BASE 0x60200000
29 #define CONFIG_SYS_INIT_SP_ADDR 0x60400000
30 #define CONFIG_SYS_LOAD_ADDR 0x60800800
32 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
34 #define CONFIG_ROCKUSB_G_DNL_PID 0x310B
36 #define CONFIG_SPL_TEXT_BASE 0x10080800
38 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
42 #define CONFIG_SPL_STACK 0x10087fff
[all …]
H A Drv1108_common.h16 #define CONFIG_SYS_SDRAM_BASE 0x60000000
17 #define SDRAM_MAX_SIZE 0x80000000
18 #define CONFIG_SYS_TEXT_BASE 0x60000000
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000)
20 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
23 #define CONFIG_SPL_STACK 0x10080700
24 #define CONFIG_SPL_TEXT_BASE 0x10080800
25 #define CONFIG_SPL_MAX_SIZE 0x4000
28 #define CONFIG_SPL_BSS_MAX_SIZE 0x100
30 #define CONFIG_ROCKUSB_G_DNL_PID 0x110A
[all …]
H A Drk322x_common.h19 #define CONFIG_SYS_TEXT_BASE 0x60200000
20 #define CONFIG_SYS_INIT_SP_ADDR 0x60400000
21 #define CONFIG_SYS_LOAD_ADDR 0x61800800
22 #define CONFIG_SPL_TEXT_BASE 0x60000000
24 #define GICD_BASE 0x32011000
25 #define GICC_BASE 0x32012000
29 #define CONFIG_ROCKUSB_G_DNL_PID 0x320B
34 #define CONFIG_SYS_SDRAM_BASE 0x60000000
36 #define SDRAM_MAX_SIZE 0x80000000
45 "scriptaddr=0x60000000\0" \
[all …]
H A Drk3066_common.h19 #define CONFIG_SYS_SDRAM_BASE 0x60000000
21 #define SDRAM_MAX_SIZE 0x80000000
25 #define CONFIG_SYS_TEXT_BASE 0x60408000
26 #define CONFIG_SYS_INIT_SP_ADDR 0x78000000
27 #define CONFIG_SYS_LOAD_ADDR 0x70800800
34 #define CONFIG_ROCKUSB_G_DNL_PID 0x300A
37 #define CONFIG_SPL_TEXT_BASE 0x10080C04
38 #define CONFIG_SPL_STACK 0x1008FFFF
40 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
43 #define CONFIG_SPL_MAX_SIZE 0x32000
[all …]
H A Dedb93xx.h39 #define CONFIG_ENV_SECT_SIZE 0x00020000
43 #define CONFIG_ENV_SECT_SIZE 0x00020000
47 #define CONFIG_ENV_SECT_SIZE 0x00020000
51 #define CONFIG_ENV_SECT_SIZE 0x00040000
55 #define CONFIG_ENV_SECT_SIZE 0x00020000
59 #define CONFIG_ENV_SECT_SIZE 0x00040000
63 #define CONFIG_ENV_SECT_SIZE 0x00040000
67 #define CONFIG_ENV_SECT_SIZE 0x00020000
84 #define CONFIG_CONS_INDEX 0
87 #define CONFIG_SYS_SERIAL0 0x808C0000
[all …]
H A Drk3128_common.h18 #define CONFIG_SYS_TEXT_BASE 0x60000000
19 #define CONFIG_SYS_INIT_SP_ADDR 0x60300000
20 #define CONFIG_SYS_LOAD_ADDR 0x60800800
22 #define GICC_BASE 0x1013A000
23 #define GICD_BASE 0x10139000
27 #define CONFIG_ROCKUSB_G_DNL_PID 0x310C
40 #define CONFIG_SYS_SDRAM_BASE 0x60000000
41 #define SDRAM_MAX_SIZE 0x80000000
54 "scriptaddr1=0x60500000\0" \
55 "pxefile_addr1_r=0x60600000\0" \
[all …]
H A Dve8313.h25 #define CONFIG_SYS_TEXT_BASE 0xfe000000
39 #define CONFIG_SYS_IMMR 0xE0000000
41 #define CONFIG_SYS_MEMTEST_START 0x00001000
42 #define CONFIG_SYS_MEMTEST_END 0x07000000
54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69 /* 0x80840102 */
71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
73 | (0 << TIMING_CFG0_WRT_SHIFT) \
80 /* 0x0e720802 */
[all …]
H A Dcalimain.h32 #define CONFIG_SYS_TEXT_BASE 0x60000000
40 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
41 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
46 #define CONFIG_SYS_DV_CLKMODE 0
48 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
49 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
50 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
51 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
52 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
54 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dbcmdevs_legacy.h28 #define BCM_DNGL_BL_PID_4322 0xbd13
29 #define BCM_DNGL_BL_PID_4319 0xbd16
30 #define BCM_DNGL_BL_PID_43236 0xbd17
31 #define BCM_DNGL_BL_PID_43143 0xbd1e
32 #define BCM_DNGL_BL_PID_43242 0xbd1f
33 #define BCM_DNGL_BL_PID_4350 0xbd23
34 #define BCM_DNGL_BL_PID_43569 0xbd27
37 #define BCM4335_D11AC_ID 0x43ae
38 #define BCM4335_D11AC2G_ID 0x43af
39 #define BCM4335_D11AC5G_ID 0x43b0
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Dbcmdevs_legacy.h28 #define BCM_DNGL_BL_PID_4322 0xbd13
29 #define BCM_DNGL_BL_PID_4319 0xbd16
30 #define BCM_DNGL_BL_PID_43236 0xbd17
31 #define BCM_DNGL_BL_PID_43143 0xbd1e
32 #define BCM_DNGL_BL_PID_43242 0xbd1f
33 #define BCM_DNGL_BL_PID_4350 0xbd23
34 #define BCM_DNGL_BL_PID_43569 0xbd27
37 #define BCM4335_D11AC_ID 0x43ae
38 #define BCM4335_D11AC2G_ID 0x43af
39 #define BCM4335_D11AC5G_ID 0x43b0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
49 shirq: interrupt-controller@0x50000000 {
[all …]
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
H A Dep7209.dtsi26 #address-cells = <0>;
27 #size-cells = <0>;
45 reg = <0x80000000 0xc000>;
51 reg = <0x80000000 0x4000>;
58 reg = <0x80000000 0x1 0x80000040 0x1>;
65 reg = <0x80000001 0x1 0x80000041 0x1>;
72 reg = <0x80000003 0x1 0x80000043 0x1>;
79 reg = <0x80000083 0x1 0x800000c3 0x1>;
86 reg = <0x80000100 0x80>;
94 reg = <0x80000180 0x80>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsp9860g-1h10.dts29 reg = <0x0 0x80000000 0 0x60000000>,
30 <0x1 0x80000000 0 0x60000000>;
50 ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
56 <3680000 10>, <3605000 5>, <3400000 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dxilinx-pcie.txt28 address. The value must be 0.
47 reg = < 0x50000000 0x1000000 >;
49 interrupts = < 0 52 4 >;
50 interrupt-map-mask = <0 0 0 7>;
51 interrupt-map = <0 0 0 1 &pcie_intc 1>,
52 <0 0 0 2 &pcie_intc 2>,
53 <0 0 0 3 &pcie_intc 3>,
54 <0 0 0 4 &pcie_intc 4>;
55 ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
59 #address-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dpci-rc32434.c36 #define PCI_ACCESS_READ 0
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
62 .start = 0x60000000,
63 .end = 0x6FFFFFFF,
72 .start = 0x18800000,
73 .end = 0x188FFFFF,
97 .mem_offset = 0,
98 .io_offset = 0,
105 #define PCI_ENDIAN_FLAG 0
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
H A Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dkeystone-k2e.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
57 reg = <0x2620750 24>;
65 reg = <0x25000000 0x10000>;
76 reg = <0x25010000 0x70000>;
86 gpio,syscon-dev = <&devctrl 0x240>;
95 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
96 ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
97 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
[all …]
/OK3568_Linux_fs/kernel/arch/x86/realmode/rm/
H A Dreboot.S17 * This code is called with the restart type (0 = BIOS, 1 = APM) in
87 * actual BIOS entry point, anyway (that is at 0xfffffff0).
99 andl $0x00000011, %edx
100 orl $0x60000000, %edx
104 testl $0x60000000, %edx /* If no cache bits -> no wbinvd */
108 andb $0x10, %dl
116 movw $0x1000, %ax
118 movw $0xf000, %sp
119 movw $0x5307, %ax
120 movw $0x0001, %bx
[all …]

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