1 /* 2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_RK3036_COMMON_H 7 #define __CONFIG_RK3036_COMMON_H 8 9 #include <asm/arch/hardware.h> 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (20 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 16 17 #define CONFIG_SPL_FRAMEWORK 18 19 #define CONFIG_SYS_NS16550_SERIAL 20 #define CONFIG_SYS_NS16550_MEM32 21 #define CONFIG_SYS_TEXT_BASE 0x60200000 22 #define CONFIG_SYS_INIT_SP_ADDR 0x60400000 23 #define CONFIG_SYS_LOAD_ADDR 0x61800800 24 #define CONFIG_SPL_TEXT_BASE 0x60000000 25 26 #define CONFIG_TPL_STACK 0x10081fff 27 #define CONFIG_TPL_TEXT_BASE 0x10081000 28 29 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) 30 #define CONFIG_ROCKCHIP_CHIP_TAG "RK30" 31 #define CONFIG_ROCKUSB_G_DNL_PID 0x301A 32 33 /* MMC/SD IP block */ 34 #define CONFIG_BOUNCE_BUFFER 35 36 #define CONFIG_SYS_SDRAM_BASE 0x60000000 37 #define SDRAM_BANK_SIZE (512UL << 20UL) 38 #define SDRAM_MAX_SIZE 0x80000000 39 40 #define CONFIG_SPI_FLASH_GIGADEVICE 41 42 #ifndef CONFIG_SPL_BUILD 43 /* usb otg */ 44 45 /* usb mass storage */ 46 #define CONFIG_USB_FUNCTION_MASS_STORAGE 47 #define CONFIG_CMD_USB_MASS_STORAGE 48 49 /* memory <= 128M board */ 50 #define ENV_MEM_LAYOUT_SETTINGS1 \ 51 "scriptaddr1=0x60000000\0" \ 52 "pxefile_addr1_r=0x60100000\0" \ 53 "fdt_addr1_r=0x61f00000\0" \ 54 "kernel_addr1_r=0x62000000\0" \ 55 "ramdisk_addr1_r=0x64000000\0" 56 57 #define ENV_MEM_LAYOUT_SETTINGS \ 58 "scriptaddr=0x60000000\0" \ 59 "pxefile_addr_r=0x60100000\0" \ 60 "fdt_addr_r=0x68300000\0" \ 61 "kernel_addr_r=0x62000000\0" \ 62 "ramdisk_addr_r=0x6a200000\0" 63 64 #include <config_distro_bootcmd.h> 65 66 #define CONFIG_EXTRA_ENV_SETTINGS \ 67 "partitions=" PARTS_DEFAULT \ 68 ENV_MEM_LAYOUT_SETTINGS \ 69 ENV_MEM_LAYOUT_SETTINGS1 \ 70 RKIMG_DET_BOOTDEV \ 71 BOOTENV 72 #endif 73 74 #define CONFIG_PREBOOT 75 76 #endif 77