1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/dts-v1/; 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include <dt-bindings/clock/clps711x-clock.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <1>; 10*4882a593Smuzhiyun model = "Cirrus Logic EP7209"; 11*4882a593Smuzhiyun compatible = "cirrus,ep7209"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun gpio0 = &porta; 15*4882a593Smuzhiyun gpio1 = &portb; 16*4882a593Smuzhiyun gpio3 = &portd; 17*4882a593Smuzhiyun gpio4 = &porte; 18*4882a593Smuzhiyun serial0 = &uart1; 19*4882a593Smuzhiyun serial1 = &uart2; 20*4882a593Smuzhiyun spi0 = &spi; 21*4882a593Smuzhiyun timer0 = &timer1; 22*4882a593Smuzhiyun timer1 = &timer2; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpus { 26*4882a593Smuzhiyun #address-cells = <0>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun cpu { 30*4882a593Smuzhiyun device_type = "cpu"; 31*4882a593Smuzhiyun compatible = "arm,arm720t"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun soc { 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun compatible = "simple-bus"; 39*4882a593Smuzhiyun interrupt-parent = <&intc>; 40*4882a593Smuzhiyun ranges; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun clks: clks@80000000 { 43*4882a593Smuzhiyun #clock-cells = <1>; 44*4882a593Smuzhiyun compatible = "cirrus,ep7209-clk"; 45*4882a593Smuzhiyun reg = <0x80000000 0xc000>; 46*4882a593Smuzhiyun startup-frequency = <73728000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun intc: intc@80000000 { 50*4882a593Smuzhiyun compatible = "cirrus,ep7209-intc"; 51*4882a593Smuzhiyun reg = <0x80000000 0x4000>; 52*4882a593Smuzhiyun interrupt-controller; 53*4882a593Smuzhiyun #interrupt-cells = <1>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun porta: gpio@80000000 { 57*4882a593Smuzhiyun compatible = "cirrus,ep7209-gpio"; 58*4882a593Smuzhiyun reg = <0x80000000 0x1 0x80000040 0x1>; 59*4882a593Smuzhiyun gpio-controller; 60*4882a593Smuzhiyun #gpio-cells = <2>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun portb: gpio@80000001 { 64*4882a593Smuzhiyun compatible = "cirrus,ep7209-gpio"; 65*4882a593Smuzhiyun reg = <0x80000001 0x1 0x80000041 0x1>; 66*4882a593Smuzhiyun gpio-controller; 67*4882a593Smuzhiyun #gpio-cells = <2>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun portd: gpio@80000003 { 71*4882a593Smuzhiyun compatible = "cirrus,ep7209-gpio"; 72*4882a593Smuzhiyun reg = <0x80000003 0x1 0x80000043 0x1>; 73*4882a593Smuzhiyun gpio-controller; 74*4882a593Smuzhiyun #gpio-cells = <2>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun porte: gpio@80000083 { 78*4882a593Smuzhiyun compatible = "cirrus,ep7209-gpio"; 79*4882a593Smuzhiyun reg = <0x80000083 0x1 0x800000c3 0x1>; 80*4882a593Smuzhiyun gpio-controller; 81*4882a593Smuzhiyun #gpio-cells = <2>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun syscon1: syscon@80000100 { 85*4882a593Smuzhiyun compatible = "cirrus,ep7209-syscon1", "syscon"; 86*4882a593Smuzhiyun reg = <0x80000100 0x80>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun bus: bus@80000180 { 90*4882a593Smuzhiyun #address-cells = <2>; 91*4882a593Smuzhiyun #size-cells = <1>; 92*4882a593Smuzhiyun compatible = "cirrus,ep7209-bus", "simple-bus"; 93*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_BUS>; 94*4882a593Smuzhiyun reg = <0x80000180 0x80>; 95*4882a593Smuzhiyun ranges = < 96*4882a593Smuzhiyun 0 0 0x00000000 0x10000000 97*4882a593Smuzhiyun 1 0 0x10000000 0x10000000 98*4882a593Smuzhiyun 2 0 0x20000000 0x10000000 99*4882a593Smuzhiyun 3 0 0x30000000 0x10000000 100*4882a593Smuzhiyun 4 0 0x40000000 0x10000000 101*4882a593Smuzhiyun 5 0 0x50000000 0x10000000 102*4882a593Smuzhiyun 6 0 0x60000000 0x0000c000 103*4882a593Smuzhiyun 7 0 0x70000000 0x00000080 104*4882a593Smuzhiyun >; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun fb: fb@800002c0 { 108*4882a593Smuzhiyun compatible = "cirrus,ep7209-fb"; 109*4882a593Smuzhiyun reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; 110*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_BUS>; 111*4882a593Smuzhiyun status = "disabled"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun timer1: timer@80000300 { 115*4882a593Smuzhiyun compatible = "cirrus,ep7209-timer"; 116*4882a593Smuzhiyun reg = <0x80000300 0x4>; 117*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_TIMER1>; 118*4882a593Smuzhiyun interrupts = <8>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun timer2: timer@80000340 { 122*4882a593Smuzhiyun compatible = "cirrus,ep7209-timer"; 123*4882a593Smuzhiyun reg = <0x80000340 0x4>; 124*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_TIMER2>; 125*4882a593Smuzhiyun interrupts = <9>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun pwm: pwm@80000400 { 129*4882a593Smuzhiyun compatible = "cirrus,ep7209-pwm"; 130*4882a593Smuzhiyun reg = <0x80000400 0x4>; 131*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_PWM>; 132*4882a593Smuzhiyun #pwm-cells = <1>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun uart1: uart@80000480 { 136*4882a593Smuzhiyun compatible = "cirrus,ep7209-uart"; 137*4882a593Smuzhiyun reg = <0x80000480 0x80>; 138*4882a593Smuzhiyun interrupts = <12 13>; 139*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_UART>; 140*4882a593Smuzhiyun syscon = <&syscon1>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun spi: spi@80000500 { 144*4882a593Smuzhiyun #address-cells = <1>; 145*4882a593Smuzhiyun #size-cells = <0>; 146*4882a593Smuzhiyun compatible = "cirrus,ep7209-spi"; 147*4882a593Smuzhiyun reg = <0x80000500 0x4>; 148*4882a593Smuzhiyun interrupts = <15>; 149*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_SPI>; 150*4882a593Smuzhiyun status = "disabled"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun syscon2: syscon@80001100 { 154*4882a593Smuzhiyun compatible = "cirrus,ep7209-syscon2", "syscon"; 155*4882a593Smuzhiyun reg = <0x80001100 0x80>; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun uart2: uart@80001480 { 159*4882a593Smuzhiyun compatible = "cirrus,ep7209-uart"; 160*4882a593Smuzhiyun reg = <0x80001480 0x80>; 161*4882a593Smuzhiyun interrupts = <28 29>; 162*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_UART>; 163*4882a593Smuzhiyun syscon = <&syscon2>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun dai: dai@80002000 { 167*4882a593Smuzhiyun #sound-dai-cells = <0>; 168*4882a593Smuzhiyun compatible = "cirrus,ep7209-dai"; 169*4882a593Smuzhiyun reg = <0x80002000 0x604>; 170*4882a593Smuzhiyun clocks = <&clks CLPS711X_CLK_PLL>; 171*4882a593Smuzhiyun clock-names = "pll"; 172*4882a593Smuzhiyun interrupts = <32>; 173*4882a593Smuzhiyun status = "disabled"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun syscon3: syscon@80002200 { 177*4882a593Smuzhiyun compatible = "cirrus,ep7209-syscon3", "syscon"; 178*4882a593Smuzhiyun reg = <0x80002200 0x40>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun mctrl: mctrl { 183*4882a593Smuzhiyun compatible = "cirrus,ep7209-mctrl-gpio"; 184*4882a593Smuzhiyun gpio-controller; 185*4882a593Smuzhiyun #gpio-cells = <2>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun}; 188