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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_arria10.h209 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
211 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
213 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
215 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
217 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
219 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
221 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
230 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
244 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dbcm2837.dtsi7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 reg = <0x40000000 0x100>;
23 interrupts = <0>, // PHYS_SECURE_PPI
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
39 cpu-release-addr = <0x0 0x000000d8>;
47 cpu-release-addr = <0x0 0x000000e0>;
[all …]
H A Dbcm2836.dtsi7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 reg = <0x40000000 0x100>;
29 interrupts = <0>, // PHYS_SECURE_PPI
38 #size-cells = <0>;
40 v7_cpu0: cpu@0 {
43 reg = <0xf00>;
50 reg = <0xf01>;
57 reg = <0xf02>;
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm2836.dtsi10 ranges = <0x7e000000 0x3f000000 0x1000000>,
11 <0x40000000 0x40000000 0x00001000>;
12 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
16 reg = <0x40000000 0x100>;
32 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
41 #size-cells = <0>;
44 v7_cpu0: cpu@0 {
47 reg = <0xf00>;
54 reg = <0xf01>;
61 reg = <0xf02>;
[all …]
H A Dbcm2837.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
55 cpu-release-addr = <0x0 0x000000d8>;
56 d-cache-size = <0x8000>;
[all …]
H A Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
H A Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
89 reg = <0>; /* Chip select 0 */
97 partition@0 {
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mm/
H A Dproc-arm740.S37 mrc p15, 0, r0, c1, c0, 0
38 bic r0, r0, #0x3f000000 @ bank/f/lock/s
39 bic r0, r0, #0x0000000c @ w-buffer/cache
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mov ip, #0
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
53 bic ip, ip, #0x0000000c @ ............wc..
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
61 mov r0, #0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dmac.h30 AR_RTSCTSQual##_index : 0))
34 AR_2040_##_index : 0) \
36 AR_GI##_index : 0) \
38 AR_STBC##_index : 0) \
69 #define ATH9K_TXERR_XRETRY 0x01
70 #define ATH9K_TXERR_FILT 0x02
71 #define ATH9K_TXERR_FIFO 0x04
72 #define ATH9K_TXERR_XTXOP 0x08
73 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
74 #define ATH9K_TX_ACKED 0x20
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/OK3568_Linux_fs/kernel/drivers/thermal/qcom/
H A Dtsens-v0_1.c10 #define SROT_CTRL_OFF 0x0000
13 #define TM_INT_EN_OFF 0x0000
14 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15 #define TM_Sn_STATUS_OFF 0x0030
16 #define TM_TRDY_OFF 0x005c
19 #define MSM8916_BASE0_MASK 0x0000007f
20 #define MSM8916_BASE1_MASK 0xfe000000
21 #define MSM8916_BASE0_SHIFT 0
24 #define MSM8916_S0_P1_MASK 0x00000f80
25 #define MSM8916_S1_P1_MASK 0x003e0000
[all …]
/OK3568_Linux_fs/kernel/include/linux/bcma/
H A Dbcma_driver_mips.h5 #define BCMA_MIPS_IPSFLAG 0x0F08
7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000
21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
22 #define BCMA_MIPS_MIPS74K_BIST 0x000C
23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8712/
H A Drtl8712_security_bitdef.h14 #define _SECCAM_ADR_MSK 0x000000FF
15 #define _SECCAM_ADR_SHT 0
20 #define _SEC_CONFIG_MSK 0x3F000000
22 #define _SEC_KEYCONTENT_MSK 0x00FFFFFF
23 #define _SEC_KEYCONTENT_SHT 0
31 #define _TXUSEDK BIT(0)
/OK3568_Linux_fs/kernel/drivers/net/ethernet/renesas/
H A Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/nwfpe/
H A Dfpopcode.c19 { .high = 0x0000, .low = 0x0000000000000000ULL},/* extended 0.0 */
20 { .high = 0x3fff, .low = 0x8000000000000000ULL},/* extended 1.0 */
21 { .high = 0x4000, .low = 0x8000000000000000ULL},/* extended 2.0 */
22 { .high = 0x4000, .low = 0xc000000000000000ULL},/* extended 3.0 */
23 { .high = 0x4001, .low = 0x8000000000000000ULL},/* extended 4.0 */
24 { .high = 0x4001, .low = 0xa000000000000000ULL},/* extended 5.0 */
25 { .high = 0x3ffe, .low = 0x8000000000000000ULL},/* extended 0.5 */
26 { .high = 0x4002, .low = 0xa000000000000000ULL},/* extended 10.0 */
31 0x0000000000000000ULL, /* double 0.0 */
32 0x3ff0000000000000ULL, /* double 1.0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/OK3568_Linux_fs/kernel/arch/mips/math-emu/
H A Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/OK3568_Linux_fs/u-boot/include/
H A Dmpc106.h15 #define PCIDEVID_MPC106 0x0
20 #define MPC106_REG 0x80000000
23 #define MPC106_REG_ADDR 0x80000cf8
24 #define MPC106_REG_DATA 0x80000cfc
25 #define MPC106_ISA_IO_PHYS 0x80000000
26 #define MPC106_ISA_IO_BUS 0x00000000
27 #define MPC106_ISA_IO_SIZE 0x00800000
28 #define MPC106_PCI_IO_PHYS 0x81000000
29 #define MPC106_PCI_IO_BUS 0x01000000
30 #define MPC106_PCI_IO_SIZE 0x3e800000
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/fpsp040/
H A Dsatanh.S38 | atan(X) := sgn / (+0).
41 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
71 andil #0x7FFFFFFF,%d0
72 cmpil #0x3FFF8000,%d0
82 fadds #0x3F800000,%fp1 | ...1-Y
85 andil #0x80000000,%d0
86 oril #0x3F000000,%d0 | ...SIGN(X)*HALF
99 fcmps #0x3F800000,%fp0

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