1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include "bcm283x.dtsi" 3*4882a593Smuzhiyun#include "bcm2835-common.dtsi" 4*4882a593Smuzhiyun#include "bcm2835-rpi-common.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun compatible = "brcm,bcm2836"; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun soc { 10*4882a593Smuzhiyun ranges = <0x7e000000 0x3f000000 0x1000000>, 11*4882a593Smuzhiyun <0x40000000 0x40000000 0x00001000>; 12*4882a593Smuzhiyun dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun local_intc: local_intc@40000000 { 15*4882a593Smuzhiyun compatible = "brcm,bcm2836-l1-intc"; 16*4882a593Smuzhiyun reg = <0x40000000 0x100>; 17*4882a593Smuzhiyun interrupt-controller; 18*4882a593Smuzhiyun #interrupt-cells = <2>; 19*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun arm-pmu { 24*4882a593Smuzhiyun compatible = "arm,cortex-a7-pmu"; 25*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 26*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun timer { 30*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 31*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 32*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 33*4882a593Smuzhiyun <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 34*4882a593Smuzhiyun <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 35*4882a593Smuzhiyun <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 36*4882a593Smuzhiyun always-on; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpus: cpus { 40*4882a593Smuzhiyun #address-cells = <1>; 41*4882a593Smuzhiyun #size-cells = <0>; 42*4882a593Smuzhiyun enable-method = "brcm,bcm2836-smp"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun v7_cpu0: cpu@0 { 45*4882a593Smuzhiyun device_type = "cpu"; 46*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 47*4882a593Smuzhiyun reg = <0xf00>; 48*4882a593Smuzhiyun clock-frequency = <800000000>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun v7_cpu1: cpu@1 { 52*4882a593Smuzhiyun device_type = "cpu"; 53*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 54*4882a593Smuzhiyun reg = <0xf01>; 55*4882a593Smuzhiyun clock-frequency = <800000000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun v7_cpu2: cpu@2 { 59*4882a593Smuzhiyun device_type = "cpu"; 60*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 61*4882a593Smuzhiyun reg = <0xf02>; 62*4882a593Smuzhiyun clock-frequency = <800000000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun v7_cpu3: cpu@3 { 66*4882a593Smuzhiyun device_type = "cpu"; 67*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 68*4882a593Smuzhiyun reg = <0xf03>; 69*4882a593Smuzhiyun clock-frequency = <800000000>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun/* Make the BCM2835-style global interrupt controller be a child of the 75*4882a593Smuzhiyun * CPU-local interrupt controller. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun&intc { 78*4882a593Smuzhiyun compatible = "brcm,bcm2836-armctrl-ic"; 79*4882a593Smuzhiyun reg = <0x7e00b200 0x200>; 80*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 81*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&cpu_thermal { 85*4882a593Smuzhiyun coefficients = <(-538) 407000>; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun/* enable thermal sensor with the correct compatible property set */ 89*4882a593Smuzhiyun&thermal { 90*4882a593Smuzhiyun compatible = "brcm,bcm2836-thermal"; 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun}; 93