1*4882a593Smuzhiyun#include "bcm283x.dtsi" 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun compatible = "brcm,bcm2836"; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun soc { 7*4882a593Smuzhiyun ranges = <0x7e000000 0x3f000000 0x1000000>, 8*4882a593Smuzhiyun <0x40000000 0x40000000 0x00001000>; 9*4882a593Smuzhiyun dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun local_intc: local_intc { 12*4882a593Smuzhiyun compatible = "brcm,bcm2836-l1-intc"; 13*4882a593Smuzhiyun reg = <0x40000000 0x100>; 14*4882a593Smuzhiyun interrupt-controller; 15*4882a593Smuzhiyun #interrupt-cells = <1>; 16*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun timer { 21*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 22*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 23*4882a593Smuzhiyun interrupts = <0>, // PHYS_SECURE_PPI 24*4882a593Smuzhiyun <1>, // PHYS_NONSECURE_PPI 25*4882a593Smuzhiyun <3>, // VIRT_PPI 26*4882a593Smuzhiyun <2>; // HYP_PPI 27*4882a593Smuzhiyun always-on; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpus: cpus { 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <0>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun cpu0: cpu@0 { 35*4882a593Smuzhiyun device_type = "cpu"; 36*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun enable-method = "spin-table"; 39*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000d8>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cpu1: cpu@1 { 43*4882a593Smuzhiyun device_type = "cpu"; 44*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun enable-method = "spin-table"; 47*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000e0>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun cpu2: cpu@2 { 51*4882a593Smuzhiyun device_type = "cpu"; 52*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 53*4882a593Smuzhiyun reg = <2>; 54*4882a593Smuzhiyun enable-method = "spin-table"; 55*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000e8>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun cpu3: cpu@3 { 59*4882a593Smuzhiyun device_type = "cpu"; 60*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 61*4882a593Smuzhiyun reg = <3>; 62*4882a593Smuzhiyun enable-method = "spin-table"; 63*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000f0>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun/* Make the BCM2835-style global interrupt controller be a child of the 69*4882a593Smuzhiyun * CPU-local interrupt controller. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun&intc { 72*4882a593Smuzhiyun compatible = "brcm,bcm2836-armctrl-ic"; 73*4882a593Smuzhiyun reg = <0x7e00b200 0x200>; 74*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 75*4882a593Smuzhiyun interrupts = <8>; 76*4882a593Smuzhiyun}; 77