Home
last modified time | relevance | path

Searched +full:0 +full:x1f0000 (Results 1 – 25 of 105) sorted by relevance

12345

/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588-android.dtsi9 bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0";
14 reg = <0x0 0xfd10c000 0x0 0x1000>,
15 <0x0 0xfd10d000 0x0 0x1000>,
16 <0x0 0xfd10e000 0x0 0x1000>,
17 <0x0 0xfd10f000 0x0 0x1000>,
18 <0x0 0xfd12c000 0x0 0x1000>,
19 <0x0 0xfd12d000 0x0 0x1000>,
20 <0x0 0xfd12e000 0x0 0x1000>,
21 <0x0 0xfd12f000 0x0 0x1000>;
26 reg = <0x0 0xfd104000 0x0 0x1000>,
[all …]
H A Drk3528-linux.dtsi9 …bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw roo…
14 rockchip,serial-id = <0>;
15 rockchip,wake-irq = <0>;
21 pinctrl-0 = <&uart0m0_xfer>;
39 reg = <0x0 0x0 0x0 0x0>;
44 reg = <0x0 0x0 0x0 0x0>;
49 /* 0x110000 to 0x1f0000 is for ramoops */
50 reg = <0x0 0x110000 0x0 0xe0000>;
51 boot-log-size = <0x8000>; /* do not change */
52 boot-log-count = <0x1>; /* do not change */
[all …]
H A Drk3528-android.dtsi9 …rlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 driver_async_probe=dwmmc_rockchip,rockchip-drm d…
14 rockchip,serial-id = <0>;
15 rockchip,wake-irq = <0>;
21 pinctrl-0 = <&uart0m0_xfer>;
40 size = <0x0 0x00800000>;
46 reg = <0x0 0x0 0x0 0x0>;
51 reg = <0x0 0x0 0x0 0x0>;
56 /* 0x110000 to 0x1f0000 is for ramoops */
57 reg = <0x0 0x110000 0x0 0xe0000>;
58 boot-log-size = <0x8000>; /* do not change */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qualcomm/emac/
H A Demac-phy.c15 #define EMAC_MDIO_CTRL 0x001414
16 #define EMAC_PHY_STS 0x001418
17 #define EMAC_MDIO_EX_CTRL 0x001440
24 #define MDIO_CLK_SEL_BMSK 0x7000000
29 #define MDIO_REG_ADDR_BMSK 0x1f0000
31 #define MDIO_DATA_BMSK 0xffff
32 #define MDIO_DATA_SHFT 0
35 #define PHY_ADDR_BMSK 0x1f0000
38 #define MDIO_CLK_25_4 0
88 return 0; in emac_mdio_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/rc/
H A Dir-sony-decoder.c44 return 0; in ir_sony_decode()
62 data->count = 0; in ir_sony_decode()
64 return 0; in ir_sony_decode()
74 return 0; in ir_sony_decode()
88 return 0; in ir_sony_decode()
101 return 0; in ir_sony_decode()
119 device = bitrev8((data->bits << 3) & 0xF8); in ir_sony_decode()
120 subdevice = 0; in ir_sony_decode()
121 function = bitrev8((data->bits >> 4) & 0xFE); in ir_sony_decode()
128 device = bitrev8((data->bits >> 0) & 0xFF); in ir_sony_decode()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-sc7180.yaml68 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm8150.yaml66 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm8250.yaml66 reg = <0x00100000 0x1f0000>;
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h12 #define ROM_SW_INFO_ADDR 0x000001E8
13 #define ROMCP_ARB_BASE_ADDR 0x00000000
14 #define ROMCP_ARB_END_ADDR 0x00017FFF
16 #define CAAM_ARB_BASE_ADDR 0x00100000
17 #define CAAM_ARB_END_ADDR 0x00107FFF
18 #define GIC400_ARB_BASE_ADDR 0x31000000
19 #define GIC400_ARB_END_ADDR 0x31007FFF
20 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
21 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
22 #define M4_BOOTROM_BASE_ADDR 0x00180000
[all …]
/OK3568_Linux_fs/kernel/Documentation/i2c/
H A Di2c-stub.rst26 explicitly by setting the respective bits (0x03000000) in the functionality
52 value 0x1f0000 would only enable the quick, byte and byte data
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/
H A Dphydm_cck_pd.c36 PHYDM_DBG(p_dm, DBG_CCKPD, ("[New] pd_th=0x%x, cs_ratio=0x%x\n\n", cca_th, cca_th_aaa)); in phydm_write_cck_cca_th_new_cs_ratio()
41 odm_set_bb_reg(p_dm, 0xa08, 0xf0000, cca_th); in phydm_write_cck_cca_th_new_cs_ratio()
49 odm_set_bb_reg(p_dm, 0xaa8, 0x1f0000, cca_th_aaa); in phydm_write_cck_cca_th_new_cs_ratio()
65 PHYDM_DBG(p_dm, DBG_CCKPD, ("New cck_cca_th=((0x%x))\n\n", cca_th)); in phydm_write_cck_cca_th()
90 /*val_buf[0]: 0xa0a*/ in phydm_set_cckpd_val()
91 /*val_buf[1]: 0xaaa*/ in phydm_set_cckpd_val()
94 phydm_write_cck_cca_th_new_cs_ratio(p_dm, (u8)val_buf[0], (u8)val_buf[1]); in phydm_set_cckpd_val()
96 phydm_write_cck_cca_th(p_dm, (u8)val_buf[0]); in phydm_set_cckpd_val()
114 phydm_write_cck_cca_th(p_dm, 0x43); in phydm_stop_cck_pd_th()
127 #if 0/*(DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))*/ in phydm_stop_cck_pd_th()
[all …]
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/lirc/lirc/
H A Dlircd.conf21 pre_data 0x54
25 MUTE 0x70
26 EXIT 0xA8
27 POWER 0xF0
28 CHANNEL_UP 0x50
29 CHANNEL_DOWN 0xD0
30 VOLUME_UP 0x30
31 VOLUME_DOWN 0xB0
32 OK 0x98
33 FAVORITES 0x04
[all …]
/OK3568_Linux_fs/kernel/drivers/net/mdio/
H A Dmdio-moxart.c16 #define REG_PHY_CTRL 0
22 #define REGAD_MASK 0x3e00000
23 #define PHYAD_MASK 0x1f0000
24 #define MIIRDATA_MASK 0xffff
27 #define MIIWDATA_MASK 0xffff
36 u32 ctrl = 0; in moxart_mdio_read()
54 } while (count > 0); in moxart_mdio_read()
65 u32 ctrl = 0; in moxart_mdio_write()
82 return 0; in moxart_mdio_write()
86 } while (count > 0); in moxart_mdio_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/
H A Drk628_combrxphy.c28 #define REG(x) ((x) + 0x10000)
29 #define COMBRXPHY_MAX_REGISTER REG(0x6790)
40 MODULE_PARM_DESC(debug, "debug level (0-1)");
45 data_in[0] = data[0]; in rk628_combrxphy_set_data_of_round()
70 u32 cnt = 0; in rk628_combrxphy_max_zero_of_round()
71 u32 max_cnt = 0; in rk628_combrxphy_max_zero_of_round()
72 u32 max_v = 0; in rk628_combrxphy_max_zero_of_round()
74 if (debug > 0) { in rk628_combrxphy_max_zero_of_round()
81 for (i = 0; i < MAX_DATA_NUM; i++) { in rk628_combrxphy_max_zero_of_round()
86 for (i = 0; i < MAX_DATA_NUM; i++) { in rk628_combrxphy_max_zero_of_round()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_3_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drv1106_pm.h9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
20 #define RV1106_PERISGRF_OFFSET 0x70000
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_combrxphy.c20 #define COMBRXPHY_MAX_REGISTER COMBRX_REG(0x6790)
43 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val); in rk628_combrxphy_try_clk_detect()
45 val = val & 0xfffffff6; in rk628_combrxphy_try_clk_detect()
46 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val); in rk628_combrxphy_try_clk_detect()
51 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val); in rk628_combrxphy_try_clk_detect()
53 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val); in rk628_combrxphy_try_clk_detect()
55 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val); in rk628_combrxphy_try_clk_detect()
56 val = val & 0xfffffeff; in rk628_combrxphy_try_clk_detect()
57 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val); in rk628_combrxphy_try_clk_detect()
59 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val); in rk628_combrxphy_try_clk_detect()
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_combrxphy.c28 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val); in rk628_combrxphy_try_clk_detect()
30 val = val & 0xfffffff6; in rk628_combrxphy_try_clk_detect()
31 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val); in rk628_combrxphy_try_clk_detect()
37 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val); in rk628_combrxphy_try_clk_detect()
39 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val); in rk628_combrxphy_try_clk_detect()
41 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val); in rk628_combrxphy_try_clk_detect()
42 val = val & 0xfffffeff; in rk628_combrxphy_try_clk_detect()
43 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val); in rk628_combrxphy_try_clk_detect()
45 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val); in rk628_combrxphy_try_clk_detect()
46 val = val & 0xfffffffe; in rk628_combrxphy_try_clk_detect()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
88 flash@0 {
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Djz4740.c23 #define JZ4740_REG_CODEC_1 0x0
24 #define JZ4740_REG_CODEC_2 0x4
44 #define JZ4740_CODEC_1_RESET BIT(0)
55 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
56 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
57 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
58 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
63 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
66 { JZ4740_REG_CODEC_1, 0x021b2302 },
67 { JZ4740_REG_CODEC_2, 0x00170803 },
[all …]

12345