1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* MOXA ART Ethernet (RTL8201CP) MDIO interface driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/mutex.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_mdio.h>
13*4882a593Smuzhiyun #include <linux/phy.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define REG_PHY_CTRL 0
17*4882a593Smuzhiyun #define REG_PHY_WRITE_DATA 4
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* REG_PHY_CTRL */
20*4882a593Smuzhiyun #define MIIWR BIT(27) /* init write sequence (auto cleared)*/
21*4882a593Smuzhiyun #define MIIRD BIT(26)
22*4882a593Smuzhiyun #define REGAD_MASK 0x3e00000
23*4882a593Smuzhiyun #define PHYAD_MASK 0x1f0000
24*4882a593Smuzhiyun #define MIIRDATA_MASK 0xffff
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* REG_PHY_WRITE_DATA */
27*4882a593Smuzhiyun #define MIIWDATA_MASK 0xffff
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct moxart_mdio_data {
30*4882a593Smuzhiyun void __iomem *base;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
moxart_mdio_read(struct mii_bus * bus,int mii_id,int regnum)33*4882a593Smuzhiyun static int moxart_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct moxart_mdio_data *data = bus->priv;
36*4882a593Smuzhiyun u32 ctrl = 0;
37*4882a593Smuzhiyun unsigned int count = 5;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s\n", __func__);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun ctrl |= MIIRD | ((mii_id << 16) & PHYAD_MASK) |
42*4882a593Smuzhiyun ((regnum << 21) & REGAD_MASK);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun writel(ctrl, data->base + REG_PHY_CTRL);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun do {
47*4882a593Smuzhiyun ctrl = readl(data->base + REG_PHY_CTRL);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (!(ctrl & MIIRD))
50*4882a593Smuzhiyun return ctrl & MIIRDATA_MASK;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun mdelay(10);
53*4882a593Smuzhiyun count--;
54*4882a593Smuzhiyun } while (count > 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s timed out\n", __func__);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return -ETIMEDOUT;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
moxart_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)61*4882a593Smuzhiyun static int moxart_mdio_write(struct mii_bus *bus, int mii_id,
62*4882a593Smuzhiyun int regnum, u16 value)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct moxart_mdio_data *data = bus->priv;
65*4882a593Smuzhiyun u32 ctrl = 0;
66*4882a593Smuzhiyun unsigned int count = 5;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s\n", __func__);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ctrl |= MIIWR | ((mii_id << 16) & PHYAD_MASK) |
71*4882a593Smuzhiyun ((regnum << 21) & REGAD_MASK);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun value &= MIIWDATA_MASK;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun writel(value, data->base + REG_PHY_WRITE_DATA);
76*4882a593Smuzhiyun writel(ctrl, data->base + REG_PHY_CTRL);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun do {
79*4882a593Smuzhiyun ctrl = readl(data->base + REG_PHY_CTRL);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (!(ctrl & MIIWR))
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun mdelay(10);
85*4882a593Smuzhiyun count--;
86*4882a593Smuzhiyun } while (count > 0);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s timed out\n", __func__);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return -ETIMEDOUT;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
moxart_mdio_reset(struct mii_bus * bus)93*4882a593Smuzhiyun static int moxart_mdio_reset(struct mii_bus *bus)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun int data, i;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun for (i = 0; i < PHY_MAX_ADDR; i++) {
98*4882a593Smuzhiyun data = moxart_mdio_read(bus, i, MII_BMCR);
99*4882a593Smuzhiyun if (data < 0)
100*4882a593Smuzhiyun continue;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun data |= BMCR_RESET;
103*4882a593Smuzhiyun if (moxart_mdio_write(bus, i, MII_BMCR, data) < 0)
104*4882a593Smuzhiyun continue;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
moxart_mdio_probe(struct platform_device * pdev)110*4882a593Smuzhiyun static int moxart_mdio_probe(struct platform_device *pdev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
113*4882a593Smuzhiyun struct mii_bus *bus;
114*4882a593Smuzhiyun struct moxart_mdio_data *data;
115*4882a593Smuzhiyun int ret, i;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun bus = mdiobus_alloc_size(sizeof(*data));
118*4882a593Smuzhiyun if (!bus)
119*4882a593Smuzhiyun return -ENOMEM;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun bus->name = "MOXA ART Ethernet MII";
122*4882a593Smuzhiyun bus->read = &moxart_mdio_read;
123*4882a593Smuzhiyun bus->write = &moxart_mdio_write;
124*4882a593Smuzhiyun bus->reset = &moxart_mdio_reset;
125*4882a593Smuzhiyun snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d-mii", pdev->name, pdev->id);
126*4882a593Smuzhiyun bus->parent = &pdev->dev;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Setting PHY_IGNORE_INTERRUPT here even if it has no effect,
129*4882a593Smuzhiyun * of_mdiobus_register() sets these PHY_POLL.
130*4882a593Smuzhiyun * Ideally, the interrupt from MAC controller could be used to
131*4882a593Smuzhiyun * detect link state changes, not polling, i.e. if there was
132*4882a593Smuzhiyun * a way phy_driver could set PHY_HAS_INTERRUPT but have that
133*4882a593Smuzhiyun * interrupt handled in ethernet drivercode.
134*4882a593Smuzhiyun */
135*4882a593Smuzhiyun for (i = 0; i < PHY_MAX_ADDR; i++)
136*4882a593Smuzhiyun bus->irq[i] = PHY_IGNORE_INTERRUPT;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun data = bus->priv;
139*4882a593Smuzhiyun data->base = devm_platform_ioremap_resource(pdev, 0);
140*4882a593Smuzhiyun if (IS_ERR(data->base)) {
141*4882a593Smuzhiyun ret = PTR_ERR(data->base);
142*4882a593Smuzhiyun goto err_out_free_mdiobus;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = of_mdiobus_register(bus, np);
146*4882a593Smuzhiyun if (ret < 0)
147*4882a593Smuzhiyun goto err_out_free_mdiobus;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun platform_set_drvdata(pdev, bus);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return 0;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun err_out_free_mdiobus:
154*4882a593Smuzhiyun mdiobus_free(bus);
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
moxart_mdio_remove(struct platform_device * pdev)158*4882a593Smuzhiyun static int moxart_mdio_remove(struct platform_device *pdev)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct mii_bus *bus = platform_get_drvdata(pdev);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun mdiobus_unregister(bus);
163*4882a593Smuzhiyun mdiobus_free(bus);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct of_device_id moxart_mdio_dt_ids[] = {
169*4882a593Smuzhiyun { .compatible = "moxa,moxart-mdio" },
170*4882a593Smuzhiyun { }
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, moxart_mdio_dt_ids);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static struct platform_driver moxart_mdio_driver = {
175*4882a593Smuzhiyun .probe = moxart_mdio_probe,
176*4882a593Smuzhiyun .remove = moxart_mdio_remove,
177*4882a593Smuzhiyun .driver = {
178*4882a593Smuzhiyun .name = "moxart-mdio",
179*4882a593Smuzhiyun .of_match_table = moxart_mdio_dt_ids,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun module_platform_driver(moxart_mdio_driver);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun MODULE_DESCRIPTION("MOXA ART MDIO interface driver");
186*4882a593Smuzhiyun MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
187*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
188