Home
last modified time | relevance | path

Searched +full:0 +full:x128 (Results 1 – 25 of 598) sorted by relevance

12345678910>>...24

/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dr8a774a1-cpg-mssr.c75 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
96 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
105 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
106 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
107 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
108 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
121 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
[all …]
H A Dr8a774b1-cpg-mssr.c93 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
94 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
95 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
96 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
102 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
118 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
248 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
H A Dr8a77965-cpg-mssr.c104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
278 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
H A Dr8a7796-cpg-mssr.c87 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
H A Dr8a774e1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
113 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
[all …]
H A Dr8a7795-cpg-mssr.c85 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
117 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
119 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
120 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
H A Dr8a779a0-cpg-mssr.c102 DEF_PLL(".pll20", CLK_PLL20, 0x0834),
103 DEF_PLL(".pll21", CLK_PLL21, 0x0838),
104 DEF_PLL(".pll30", CLK_PLL30, 0x083c),
105 DEF_PLL(".pll31", CLK_PLL31, 0x0840),
141 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
142 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
143 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
172 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_r8a779a0_cpg_clk_register()
188 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_r8a779a0_cpg_clk_register()
202 div = core->div & 0xffff; in rcar_r8a779a0_cpg_clk_register()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dsitronix,st7735r.yaml23 Adafruit 1.8" 160x128 Color TFT LCD (Product ID 358 or 618)
29 Okaya 1.44" 128x128 Color TFT LCD (E.g. Renesas YRSK-LCD-PMOD)
66 #size-cells = <0>;
68 display@0{
70 reg = <0>;
/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam335x-draco.dts45 reg = <0x4b000000 1000000>;
53 pinctrl-0 = <&gpio_mux_pins>;
57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */
58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */
59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */
60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */
61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */
67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/
68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt7622.c295 .set_ofs = 0x8,
296 .clr_ofs = 0x8,
297 .sta_ofs = 0x8,
301 .set_ofs = 0x40,
302 .clr_ofs = 0x44,
303 .sta_ofs = 0x48,
307 .set_ofs = 0x120,
308 .clr_ofs = 0x120,
309 .sta_ofs = 0x120,
313 .set_ofs = 0x128,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dqcom,qmp-usb3-dp-phy.yaml81 "^usb3-phy@[0-9a-f]+$":
109 const: 0
112 const: 0
121 "^dp-phy@[0-9a-f]+$":
139 const: 0
167 reg = <0x088e9000 0x18c>,
168 <0x088e8000 0x10>,
169 <0x088ea000 0x40>;
174 ranges = <0x0 0x088e9000 0x2000>;
190 reg = <0x200 0x128>,
[all …]
H A Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/OK3568_Linux_fs/external/camera_engine_rkaiq/rkisp_demo/demo/ae_algo_demo/
H A Dthird_party_ae_algo.cpp24 return 0; in custom_ae_init()
45 #if 0 in custom_ae_run()
50 for(int i = 0; i < 225; i++) { in custom_ae_run()
51 …MeanLuma[0] += (float)(pstAeInfo->rawae_stat[0].rawae_big.channelg_xy[i] >> 4); //channelg is 12bi… in custom_ae_run()
55 MeanLuma[0] /= 225.0f; //range:0~255 (equal to 8bit) in custom_ae_run()
56 MeanLuma[1] /= 225.0f; //range:0~255 (equal to 8bit) in custom_ae_run()
60 pstAeInfo->linear_exp.exp_real_params.integration_time, MeanLuma[0]); in custom_ae_run()
62 …pstAeInfo->hdr_exp[0].exp_real_params.analog_gain, pstAeInfo->hdr_exp[0].exp_real_params.integrati… in custom_ae_run()
64 MeanLuma[0], MeanLuma[1]); in custom_ae_run()
68 static uint32_t frmid = 0; in custom_ae_run()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c24 #define CPG_RST_MODEMR 0x0060
26 #define CPG_PLL0CR 0x00d8
27 #define CPG_PLL2CR 0x002c
28 #define CPG_PLL4CR 0x01f4
43 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
44 0x9A0, 0x9A4, 0x9A8, 0x9AC,
55 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
56 0x990, 0x994, 0x998, 0x99C,
63 #define RMSTPCR(i) (smstpcr[i] - 0x20)
66 #define MMSTPCR(i) (smstpcr[i] + 0x20)
[all …]
/OK3568_Linux_fs/u-boot/drivers/misc/
H A Drv1126-secure-otp.S9 .eabi_attribute 34, 0
25 .loc 1 172 0
27 @ args = 0, pretend = 0, frame = 0
28 @ frame_needed = 0, uses_anonymous_args = 0
31 .loc 1 175 0
37 .loc 1 165 0
42 .loc 1 178 0
43 moveq r0, #0
47 .loc 1 165 0
52 .loc 1 173 0
[all …]
/OK3568_Linux_fs/kernel/arch/x86/crypto/
H A Dcrc32-pclmul_asm.S29 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
46 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4
47 * #define CONSTANT_R1 0x154442bd4LL
49 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596
50 * #define CONSTANT_R2 0x1c6e41596LL
53 .octa 0x00000001c6e415960000000154442bd4
55 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0
56 * #define CONSTANT_R3 0x1751997d0LL
58 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e
59 * #define CONSTANT_R4 0x0ccaa009eLL
[all …]
/OK3568_Linux_fs/kernel/arch/s390/crypto/
H A Dcrc32be-vx.S39 * R3 = x128+64 mod P(x)
40 * R4 = x128 mod P(x)
51 * The righmost doubleword can be 0 to prevent contribution to the result or
57 * P(x) = 0x04C11DB7
58 * P'(x) = 0xEDB88320
62 .quad 0x08833794c, 0x0e6228b11 # R1, R2
63 .quad 0x0c5b9cd4c, 0x0e8a45605 # R3, R4
64 .quad 0x0f200aa66, 1 << 32 # R5, x32
65 .quad 0x0490d678d, 1 # R6, 1
66 .quad 0x104d101df, 0 # u
[all …]
/OK3568_Linux_fs/u-boot/arch/arc/cpu/arcv1/
H A Divt.S11 j _start /* 0 - 0x000 */
12 j memory_error /* 1 - 0x008 */
13 j instruction_error /* 2 - 0x010 */
17 j interrupt_handler /* 3:31 - 0x018:0xF8 */
20 j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
21 j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
22 j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
23 j EV_TLBProtV /* 0x118, Protection Violation (0x23)
25 j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
26 j EV_Trap /* 0x128, Trap exception (0x25) */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dstv0991_gpt.h20 u32 reserved_2[3]; /* offset 0x18--0x20*/
30 #define GPT_CR1_CEN 0x0001
34 #define GPT_PRESCALER_128 0x128
37 #define GPT_FREE_RUNNING 0xFFFF
/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]

12345678910>>...24