Lines Matching +full:0 +full:x128
24 #define CPG_RST_MODEMR 0x0060
26 #define CPG_PLL0CR 0x00d8
27 #define CPG_PLL2CR 0x002c
28 #define CPG_PLL4CR 0x01f4
43 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
44 0x9A0, 0x9A4, 0x9A8, 0x9AC,
55 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
56 0x990, 0x994, 0x998, 0x99C,
63 #define RMSTPCR(i) (smstpcr[i] - 0x20)
66 #define MMSTPCR(i) (smstpcr[i] + 0x20)
69 #define SRSTCLR(i) (0x940 + (i) * 4)
229 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
230 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
231 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
232 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
245 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
440 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
441 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
442 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
443 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
588 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
589 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
590 * 0 0 1 0 Prohibited setting
591 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
592 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
593 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
594 * 0 1 1 0 Prohibited setting
595 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
596 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
597 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
598 * 1 0 1 0 Prohibited setting
599 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
600 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
601 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
602 * 1 1 1 0 Prohibited setting
614 { 0, /* Prohibited setting */ },
618 { 0, /* Prohibited setting */ },
622 { 0, /* Prohibited setting */ },
626 { 0, /* Prohibited setting */ },
637 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
641 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
642 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
644 ((sd_fc) << 0), \
657 * 0 0 0 (1) 1 (4) 4
658 * 0 0 1 (2) 1 (4) 8
659 * 1 0 2 (4) 1 (4) 16
660 * 1 0 3 (8) 1 (4) 32
661 * 1 0 4 (16) 1 (4) 64
662 * 0 0 0 (1) 0 (2) 2
663 * 0 0 1 (2) 0 (2) 4
664 * 1 0 2 (4) 0 (2) 8
665 * 1 0 3 (8) 0 (2) 16
666 * 1 0 4 (16) 0 (2) 32
670 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
671 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
672 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
673 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
674 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
675 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
676 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
677 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
678 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
679 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
690 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_get_mod()
696 for (i = 0; i < priv->mod_clk_size; i++) { in gen3_clk_get_mod()
701 return 0; in gen3_clk_get_mod()
710 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_get_core()
716 for (i = 0; i < priv->core_clk_size; i++) { in gen3_clk_get_core()
721 return 0; in gen3_clk_get_core()
745 parent->id = ~0; /* Top-level clock */ in gen3_clk_get_parent()
752 return 0; in gen3_clk_get_parent()
758 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_endisable()
772 bitmask, 0, 100, 0); in gen3_clk_endisable()
775 return 0; in gen3_clk_endisable()
796 u32 value, mult, rate = 0; in gen3_clk_get_rate()
845 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate()
860 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate()
875 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate()
892 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { in gen3_clk_get_rate()
925 clk->id = (args->args[0] << 16) | args->args[1]; in gen3_clk_of_xlate()
927 return 0; in gen3_clk_of_xlate()
963 if (ret < 0) in gen3_clk_probe()
973 if (ret < 0) in gen3_clk_probe()
991 if (ret < 0) in gen3_clk_probe()
995 if (ret < 0) in gen3_clk_probe()
998 return 0; in gen3_clk_probe()