1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _STV0991_GPT_H 9*4882a593Smuzhiyun #define _STV0991_GPT_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch-stv0991/hardware.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct gpt_regs { 14*4882a593Smuzhiyun u32 cr1; 15*4882a593Smuzhiyun u32 cr2; 16*4882a593Smuzhiyun u32 reserved_1; 17*4882a593Smuzhiyun u32 dier; /* dma_int_en */ 18*4882a593Smuzhiyun u32 sr; /* status reg */ 19*4882a593Smuzhiyun u32 egr; /* event gen */ 20*4882a593Smuzhiyun u32 reserved_2[3]; /* offset 0x18--0x20*/ 21*4882a593Smuzhiyun u32 cnt; 22*4882a593Smuzhiyun u32 psc; 23*4882a593Smuzhiyun u32 arr; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct gpt_regs *const gpt1_regs_ptr = 27*4882a593Smuzhiyun (struct gpt_regs *) GPTIMER1_BASE_ADDR; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Timer control1 register */ 30*4882a593Smuzhiyun #define GPT_CR1_CEN 0x0001 31*4882a593Smuzhiyun #define GPT_MODE_AUTO_RELOAD (1 << 7) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Timer prescalar reg */ 34*4882a593Smuzhiyun #define GPT_PRESCALER_128 0x128 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Auto reload register for free running config */ 37*4882a593Smuzhiyun #define GPT_FREE_RUNNING 0xFFFF 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Timer, HZ specific defines */ 40*4882a593Smuzhiyun #define CONFIG_STV0991_HZ 1000 41*4882a593Smuzhiyun #define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif 44