1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Hardware-accelerated CRC-32 variants for Linux on z Systems 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Use the z/Architecture Vector Extension Facility to accelerate the 6*4882a593Smuzhiyun * computing of CRC-32 checksums. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This CRC-32 implementation algorithm processes the most-significant 9*4882a593Smuzhiyun * bit first (BE). 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Copyright IBM Corp. 2015 12*4882a593Smuzhiyun * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include <linux/linkage.h> 16*4882a593Smuzhiyun#include <asm/nospec-insn.h> 17*4882a593Smuzhiyun#include <asm/vx-insn.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* Vector register range containing CRC-32 constants */ 20*4882a593Smuzhiyun#define CONST_R1R2 %v9 21*4882a593Smuzhiyun#define CONST_R3R4 %v10 22*4882a593Smuzhiyun#define CONST_R5 %v11 23*4882a593Smuzhiyun#define CONST_R6 %v12 24*4882a593Smuzhiyun#define CONST_RU_POLY %v13 25*4882a593Smuzhiyun#define CONST_CRC_POLY %v14 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun.data 28*4882a593Smuzhiyun.align 8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun/* 31*4882a593Smuzhiyun * The CRC-32 constant block contains reduction constants to fold and 32*4882a593Smuzhiyun * process particular chunks of the input data stream in parallel. 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * For the CRC-32 variants, the constants are precomputed according to 35*4882a593Smuzhiyun * these defintions: 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * R1 = x4*128+64 mod P(x) 38*4882a593Smuzhiyun * R2 = x4*128 mod P(x) 39*4882a593Smuzhiyun * R3 = x128+64 mod P(x) 40*4882a593Smuzhiyun * R4 = x128 mod P(x) 41*4882a593Smuzhiyun * R5 = x96 mod P(x) 42*4882a593Smuzhiyun * R6 = x64 mod P(x) 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * Barret reduction constant, u, is defined as floor(x**64 / P(x)). 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun * where P(x) is the polynomial in the normal domain and the P'(x) is the 47*4882a593Smuzhiyun * polynomial in the reversed (bitreflected) domain. 48*4882a593Smuzhiyun * 49*4882a593Smuzhiyun * Note that the constant definitions below are extended in order to compute 50*4882a593Smuzhiyun * intermediate results with a single VECTOR GALOIS FIELD MULTIPLY instruction. 51*4882a593Smuzhiyun * The righmost doubleword can be 0 to prevent contribution to the result or 52*4882a593Smuzhiyun * can be multiplied by 1 to perform an XOR without the need for a separate 53*4882a593Smuzhiyun * VECTOR EXCLUSIVE OR instruction. 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials: 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * P(x) = 0x04C11DB7 58*4882a593Smuzhiyun * P'(x) = 0xEDB88320 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun.Lconstants_CRC_32_BE: 62*4882a593Smuzhiyun .quad 0x08833794c, 0x0e6228b11 # R1, R2 63*4882a593Smuzhiyun .quad 0x0c5b9cd4c, 0x0e8a45605 # R3, R4 64*4882a593Smuzhiyun .quad 0x0f200aa66, 1 << 32 # R5, x32 65*4882a593Smuzhiyun .quad 0x0490d678d, 1 # R6, 1 66*4882a593Smuzhiyun .quad 0x104d101df, 0 # u 67*4882a593Smuzhiyun .quad 0x104C11DB7, 0 # P(x) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun.previous 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun GEN_BR_THUNK %r14 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun.text 74*4882a593Smuzhiyun/* 75*4882a593Smuzhiyun * The CRC-32 function(s) use these calling conventions: 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * Parameters: 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * %r2: Initial CRC value, typically ~0; and final CRC (return) value. 80*4882a593Smuzhiyun * %r3: Input buffer pointer, performance might be improved if the 81*4882a593Smuzhiyun * buffer is on a doubleword boundary. 82*4882a593Smuzhiyun * %r4: Length of the buffer, must be 64 bytes or greater. 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun * Register usage: 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * %r5: CRC-32 constant pool base pointer. 87*4882a593Smuzhiyun * V0: Initial CRC value and intermediate constants and results. 88*4882a593Smuzhiyun * V1..V4: Data for CRC computation. 89*4882a593Smuzhiyun * V5..V8: Next data chunks that are fetched from the input buffer. 90*4882a593Smuzhiyun * 91*4882a593Smuzhiyun * V9..V14: CRC-32 constants. 92*4882a593Smuzhiyun */ 93*4882a593SmuzhiyunENTRY(crc32_be_vgfm_16) 94*4882a593Smuzhiyun /* Load CRC-32 constants */ 95*4882a593Smuzhiyun larl %r5,.Lconstants_CRC_32_BE 96*4882a593Smuzhiyun VLM CONST_R1R2,CONST_CRC_POLY,0,%r5 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Load the initial CRC value into the leftmost word of V0. */ 99*4882a593Smuzhiyun VZERO %v0 100*4882a593Smuzhiyun VLVGF %v0,%r2,0 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Load a 64-byte data chunk and XOR with CRC */ 103*4882a593Smuzhiyun VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */ 104*4882a593Smuzhiyun VX %v1,%v0,%v1 /* V1 ^= CRC */ 105*4882a593Smuzhiyun aghi %r3,64 /* BUF = BUF + 64 */ 106*4882a593Smuzhiyun aghi %r4,-64 /* LEN = LEN - 64 */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Check remaining buffer size and jump to proper folding method */ 109*4882a593Smuzhiyun cghi %r4,64 110*4882a593Smuzhiyun jl .Lless_than_64bytes 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun.Lfold_64bytes_loop: 113*4882a593Smuzhiyun /* Load the next 64-byte data chunk into V5 to V8 */ 114*4882a593Smuzhiyun VLM %v5,%v8,0,%r3 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * Perform a GF(2) multiplication of the doublewords in V1 with 118*4882a593Smuzhiyun * the reduction constants in V0. The intermediate result is 119*4882a593Smuzhiyun * then folded (accumulated) with the next data chunk in V5 and 120*4882a593Smuzhiyun * stored in V1. Repeat this step for the register contents 121*4882a593Smuzhiyun * in V2, V3, and V4 respectively. 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun VGFMAG %v1,CONST_R1R2,%v1,%v5 124*4882a593Smuzhiyun VGFMAG %v2,CONST_R1R2,%v2,%v6 125*4882a593Smuzhiyun VGFMAG %v3,CONST_R1R2,%v3,%v7 126*4882a593Smuzhiyun VGFMAG %v4,CONST_R1R2,%v4,%v8 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Adjust buffer pointer and length for next loop */ 129*4882a593Smuzhiyun aghi %r3,64 /* BUF = BUF + 64 */ 130*4882a593Smuzhiyun aghi %r4,-64 /* LEN = LEN - 64 */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun cghi %r4,64 133*4882a593Smuzhiyun jnl .Lfold_64bytes_loop 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun.Lless_than_64bytes: 136*4882a593Smuzhiyun /* Fold V1 to V4 into a single 128-bit value in V1 */ 137*4882a593Smuzhiyun VGFMAG %v1,CONST_R3R4,%v1,%v2 138*4882a593Smuzhiyun VGFMAG %v1,CONST_R3R4,%v1,%v3 139*4882a593Smuzhiyun VGFMAG %v1,CONST_R3R4,%v1,%v4 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Check whether to continue with 64-bit folding */ 142*4882a593Smuzhiyun cghi %r4,16 143*4882a593Smuzhiyun jl .Lfinal_fold 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun.Lfold_16bytes_loop: 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun VL %v2,0,,%r3 /* Load next data chunk */ 148*4882a593Smuzhiyun VGFMAG %v1,CONST_R3R4,%v1,%v2 /* Fold next data chunk */ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Adjust buffer pointer and size for folding next data chunk */ 151*4882a593Smuzhiyun aghi %r3,16 152*4882a593Smuzhiyun aghi %r4,-16 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Process remaining data chunks */ 155*4882a593Smuzhiyun cghi %r4,16 156*4882a593Smuzhiyun jnl .Lfold_16bytes_loop 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun.Lfinal_fold: 159*4882a593Smuzhiyun /* 160*4882a593Smuzhiyun * The R5 constant is used to fold a 128-bit value into an 96-bit value 161*4882a593Smuzhiyun * that is XORed with the next 96-bit input data chunk. To use a single 162*4882a593Smuzhiyun * VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to 163*4882a593Smuzhiyun * form an intermediate 96-bit value (with appended zeros) which is then 164*4882a593Smuzhiyun * XORed with the intermediate reduction result. 165*4882a593Smuzhiyun */ 166*4882a593Smuzhiyun VGFMG %v1,CONST_R5,%v1 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* 169*4882a593Smuzhiyun * Further reduce the remaining 96-bit value to a 64-bit value using a 170*4882a593Smuzhiyun * single VGFMG, the rightmost doubleword is multiplied with 0x1. The 171*4882a593Smuzhiyun * intermediate result is then XORed with the product of the leftmost 172*4882a593Smuzhiyun * doubleword with R6. The result is a 64-bit value and is subject to 173*4882a593Smuzhiyun * the Barret reduction. 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun VGFMG %v1,CONST_R6,%v1 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * The input values to the Barret reduction are the degree-63 polynomial 179*4882a593Smuzhiyun * in V1 (R(x)), degree-32 generator polynomial, and the reduction 180*4882a593Smuzhiyun * constant u. The Barret reduction result is the CRC value of R(x) mod 181*4882a593Smuzhiyun * P(x). 182*4882a593Smuzhiyun * 183*4882a593Smuzhiyun * The Barret reduction algorithm is defined as: 184*4882a593Smuzhiyun * 185*4882a593Smuzhiyun * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u 186*4882a593Smuzhiyun * 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x) 187*4882a593Smuzhiyun * 3. C(x) = R(x) XOR T2(x) mod x^32 188*4882a593Smuzhiyun * 189*4882a593Smuzhiyun * Note: To compensate the division by x^32, use the vector unpack 190*4882a593Smuzhiyun * instruction to move the leftmost word into the leftmost doubleword 191*4882a593Smuzhiyun * of the vector register. The rightmost doubleword is multiplied 192*4882a593Smuzhiyun * with zero to not contribute to the intermedate results. 193*4882a593Smuzhiyun */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */ 196*4882a593Smuzhiyun VUPLLF %v2,%v1 197*4882a593Smuzhiyun VGFMG %v2,CONST_RU_POLY,%v2 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* 200*4882a593Smuzhiyun * Compute the GF(2) product of the CRC polynomial in VO with T1(x) in 201*4882a593Smuzhiyun * V2 and XOR the intermediate result, T2(x), with the value in V1. 202*4882a593Smuzhiyun * The final result is in the rightmost word of V2. 203*4882a593Smuzhiyun */ 204*4882a593Smuzhiyun VUPLLF %v2,%v2 205*4882a593Smuzhiyun VGFMAG %v2,CONST_CRC_POLY,%v2,%v1 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun.Ldone: 208*4882a593Smuzhiyun VLGVF %r2,%v2,3 209*4882a593Smuzhiyun BR_EX %r14 210*4882a593SmuzhiyunENDPROC(crc32_be_vgfm_16) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun.previous 213