| /OK3568_Linux_fs/kernel/drivers/mfd/ |
| H A D | wm8994-core.c | 33 .id = 0,
125 if (ret < 0) { in wm8994_suspend()
129 return 0; in wm8994_suspend()
156 if (ret != 0) in wm8994_suspend()
163 if (ret != 0) in wm8994_suspend()
171 if (ret != 0) { in wm8994_suspend()
176 return 0; in wm8994_suspend()
186 return 0; in wm8994_resume()
190 if (ret != 0) { in wm8994_resume()
197 if (ret != 0) { in wm8994_resume()
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/selftests/ |
| H A D | i915_perf.c | 35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
44 return 0; in alloc_empty_config()
99 0), in test_stream()
152 return 0; in live_sanitycheck()
173 *cs++ = 0; in write_timestamp()
174 *cs++ = 0; in write_timestamp()
175 *cs++ = 0; in write_timestamp()
179 return 0; in write_timestamp()
215 for (i = 0; i < 4; i++) in live_noa_delay()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/include/ |
| H A D | hal_pg.h | 24 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
25 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
27 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
28 #define PPG_THERMAL_OFFSET_MASK 0x1F
29 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
30 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
31 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
36 #define EEPROM_TX_PWR_INX_88E 0x10
38 #define EEPROM_ChannelPlan_88E 0xB8
39 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_TX_PWR_INX_88E 0x10
34 #define EEPROM_ChannelPlan_88E 0xB8
[all …]
|
| /OK3568_Linux_fs/kernel/arch/arm/mach-tango/ |
| H A D | smc.h | 4 #define tango_set_l2_control(val) tango_smc(val, 0x102)
5 #define tango_start_aux_core(val) tango_smc(val, 0x104)
6 #define tango_set_aux_boot_addr(val) tango_smc(val, 0x105)
7 #define tango_suspend(val) tango_smc(val, 0x120)
8 #define tango_aux_core_die(val) tango_smc(val, 0x121)
9 #define tango_aux_core_kill(val) tango_smc(val, 0x122)
|
| /OK3568_Linux_fs/kernel/drivers/of/unittest-data/ |
| H A D | overlay_bad_add_dup_node.dts | 19 power_bus = < 0x1 0x2 >;
26 power_bus_emergency = < 0x101 0x102 >;
|
| /OK3568_Linux_fs/u-boot/include/ |
| H A D | micrel.h | 3 #define MII_KSZ9021_EXT_COMMON_CTRL 0x100
4 #define MII_KSZ9021_EXT_STRAP_STATUS 0x101
5 #define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
6 #define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
7 #define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
8 #define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
9 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
10 #define MII_KSZ9021_EXT_ANALOG_TEST 0x107
12 #define MII_KSZ9031_MOD_REG 0x0000
14 #define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
[all …]
|
| /OK3568_Linux_fs/kernel/include/soc/arc/ |
| H A D | timers.h | 12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
|
| /OK3568_Linux_fs/u-boot/board/renesas/r7780mp/ |
| H A D | r7780mp.h | 14 #define FPGA_BASE 0xa4000000
15 #define FPGA_IRLMSK (FPGA_BASE + 0x00)
16 #define FPGA_IRLMON (FPGA_BASE + 0x02)
17 #define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
18 #define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
19 #define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
20 #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
21 #define FPGA_RSTCTL (FPGA_BASE + 0x0C)
22 #define FPGA_PCIBD (FPGA_BASE + 0x0E)
23 #define FPGA_PCICD (FPGA_BASE + 0x10)
[all …]
|
| /OK3568_Linux_fs/kernel/arch/powerpc/include/asm/ |
| H A D | ps3gpu.h | 16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
|
| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | usb_a9g20-dab-mmx.dtsi | 21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
|
| /OK3568_Linux_fs/u-boot/arch/arc/include/asm/ |
| H A D | arcregs.h | 19 #define ARC_AUX_IDENTITY 0x04
20 #define ARC_AUX_STATUS32 0x0a
23 #define ARC_AUX_IC_IVIC 0x10
24 #define ARC_AUX_IC_CTRL 0x11
25 #define ARC_AUX_IC_IVIL 0x19
27 #define ARC_AUX_IC_PTAG 0x1E
29 #define ARC_BCR_IC_BUILD 0x77
32 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
33 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
34 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/i2c/ |
| H A D | wm8775.c | 40 #define ALC_HOLD 0x85 /* R17: use zero cross detection, ALC hold time 42.6 ms */
41 #define ALC_EN 0x100 /* R17: ALC enable */
50 u8 input; /* Last selected input (0-0xf) */
68 if (reg < 0 || reg >= TOT_REGS) { in wm8775_write()
73 for (i = 0; i < 3; i++) in wm8775_write()
75 (reg << 1) | (val >> 8), val & 0xff) == 0) in wm8775_write()
76 return 0; in wm8775_write()
85 int muted = 0 != state->mute->val; in wm8775_set_audio()
89 /* normalize ( 65535 to 0 -> 255 to 0 (+24dB to -103dB) ) */ in wm8775_set_audio()
95 wm8775_write(sd, R21, 0x0c0 | state->input); in wm8775_set_audio()
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