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/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu580.c48 } while (0)
51 RK_U32 hw_status; /* 0:corret, 1:error */
144 0x50800080, 0x00330000, 0xA1000100, 0x00660000, 0x42000200, 0x00CC0001,
145 0x84000400, 0x01980002, 0x08000800, 0x03300005, 0x10001000, 0x0660000A,
146 0x20002000, 0x0CC00014, 0x40004000, 0x19800028, 0x80008000, 0x33000050,
147 0x00010000, 0x660000A1, 0x00020000, 0xCC000142, 0xFF83FFFF, 0x000001FF
151 0, 0, 0, 0,
158 0, 2, 4, 6,
167 0, 2, 3, 4,
180 0x00000183, 0x000001b2, 0x000001e7, 0x00000223, 0x00000266, 0x000002b1, 0x00000305, 0x00000364,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-host.yaml48 const: 0x104c
51 const: 0xb00d
88 reg = <0x00 0x02900000 0x00 0x1000>,
89 <0x00 0x02907000 0x00 0x400>,
90 <0x00 0x0d000000 0x00 0x00800000>,
91 <0x00 0x10000000 0x00 0x00001000>;
102 bus-range = <0x0 0xf>;
103 vendor-id = <0x104c>;
104 device-id = <0xb00d>;
105 msi-map = <0x0 &gic_its 0x0 0x10000>;
[all …]
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-i2c.c18 #define CX18_REG_I2C_1_WR 0xf15000
19 #define CX18_REG_I2C_1_RD 0xf15008
20 #define CX18_REG_I2C_2_WR 0xf25100
21 #define CX18_REG_I2C_2_RD 0xf25108
23 #define SETSCL_BIT 0x0001
24 #define SETSDL_BIT 0x0002
25 #define GETSCL_BIT 0x0004
26 #define GETSDL_BIT 0x0008
28 #define CX18_CS5345_I2C_ADDR 0x4c
29 #define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-bcm63xx-hsspi.txt10 - #size-cells: <0>, also as required by generic SPI binding.
22 reg = <0x10001000 0x600>;
32 #size-cells = <0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dingenic,intc.yaml14 pattern: "^interrupt-controller@[0-9a-f]+$"
58 reg = <0x10001000 0x40>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,infracfg.txt38 reg = <0 0x10001000 0 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Dfsl-imx-dma.txt23 reg = <0x10001000 0x1000>;
/OK3568_Linux_fs/external/security/librkcrypto/test/c_mode/
H A Ddes_core.c42 volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; in mbedtls_zeroize()
73 0x01010400, 0x00000000, 0x00010000, 0x01010404,
74 0x01010004, 0x00010404, 0x00000004, 0x00010000,
75 0x00000400, 0x01010400, 0x01010404, 0x00000400,
76 0x01000404, 0x01010004, 0x01000000, 0x00000004,
77 0x00000404, 0x01000400, 0x01000400, 0x00010400,
78 0x00010400, 0x01010000, 0x01010000, 0x01000404,
79 0x00010004, 0x01000004, 0x01000004, 0x00010004,
80 0x00000000, 0x00000404, 0x00010404, 0x01000000,
81 0x00010000, 0x01010404, 0x00000004, 0x01010000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/dsa/
H A Db53.txt57 order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
94 reg = <0x10001000 0x1000>;
105 #size-cells = <0>;
111 #size-cells = <0>;
115 #size-cells = <0>;
117 port0@0 {
118 reg = <0>;
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_rgb.c20 rk628_i2c_write(rk628, GRF_GPIO2AB_SEL_CON, 0xffffffff); in rk628_rgb_decoder_enable()
21 rk628_i2c_write(rk628, GRF_GPIO2C_SEL_CON, 0xffff5555); in rk628_rgb_decoder_enable()
22 rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x10b010b); in rk628_rgb_decoder_enable()
25 rk628_i2c_write(rk628, GRF_GPIO2A_D0_CON, 0xffff1111); in rk628_rgb_decoder_enable()
26 rk628_i2c_write(rk628, GRF_GPIO2A_D1_CON, 0xffff1111); in rk628_rgb_decoder_enable()
27 rk628_i2c_write(rk628, GRF_GPIO2B_D0_CON, 0xffff1111); in rk628_rgb_decoder_enable()
28 rk628_i2c_write(rk628, GRF_GPIO2B_D1_CON, 0xffff1111); in rk628_rgb_decoder_enable()
29 rk628_i2c_write(rk628, GRF_GPIO2C_D0_CON, 0xffff1111); in rk628_rgb_decoder_enable()
30 rk628_i2c_write(rk628, GRF_GPIO2C_D1_CON, 0xffff1111); in rk628_rgb_decoder_enable()
31 rk628_i2c_write(rk628, GRF_GPIO3A_D0_CON, 0xffff1011); in rk628_rgb_decoder_enable()
[all …]
/OK3568_Linux_fs/u-boot/cmd/ddr_tool/stressapptest/
H A Dstressapptest.c40 0x00000001, 0x00000002, 0x00000004, 0x00000008,
41 0x00000010, 0x00000020, 0x00000040, 0x00000080,
42 0x00000100, 0x00000200, 0x00000400, 0x00000800,
43 0x00001000, 0x00002000, 0x00004000, 0x00008000,
44 0x00010000, 0x00020000, 0x00040000, 0x00080000,
45 0x00100000, 0x00200000, 0x00400000, 0x00800000,
46 0x01000000, 0x02000000, 0x04000000, 0x08000000,
47 0x10000000, 0x20000000, 0x40000000, 0x80000000,
48 0x40000000, 0x20000000, 0x10000000, 0x08000000,
49 0x04000000, 0x02000000, 0x01000000, 0x00800000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0 0x0>;
29 reg = <0x0 0x1>;
36 reg = <0x0 0x2>;
43 reg = <0x0 0x3>;
50 reg = <0 0x10003000 0 0x1000>;
64 reg = <0 0x10001000 0 0x1000>;
78 #size-cells = <0>;
80 port@0 {
[all …]
/OK3568_Linux_fs/kernel/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
24 } while (0)
27 #define PCIE_SNPS_DBI_BASE 0xf5000000
28 #define PCIE_SNPS_APB_BASE 0xfe150000
29 #define PCIE_SNPS_IATU_BASE 0xa40300000
31 #define PCI_RESBAR 0x2e8
33 #define PCIE_SNPS_DBI_BASE 0xf6000000
34 #define PCIE_SNPS_APB_BASE 0xfe280000
35 #define PCIE_SNPS_IATU_BASE 0x3c0b00000
37 #define PCI_RESBAR 0x2b8
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Ddisplay5.h14 #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
18 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00
21 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */
29 * 0x000000 - 0x020000 : SPI.SPL (128KiB)
30 * 0x020000 - 0x120000 : SPI.u-boot (1MiB)
31 * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB)
32 * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB)
33 * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB)
34 * 0x540000 - 0x1540000 : SPI.swupdate-initramfs (16MiB)
35 * 0x1540000 - 0x1640000 : SPI.factory (1MiB)
[all …]

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