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/OK3568_Linux_fs/kernel/sound/soc/sh/rcar/
H A Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
164 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
189 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
193 regf.lsb = 0; in _rsnd_gen_regmap_init()
206 return 0; in _rsnd_gen_regmap_init()
215 RSND_GEN_S_REG(SSI_MODE0, 0x800), in rsnd_gen2_probe()
216 RSND_GEN_S_REG(SSI_MODE1, 0x804), in rsnd_gen2_probe()
217 RSND_GEN_S_REG(SSI_MODE2, 0x808), in rsnd_gen2_probe()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
68 return 0; in rv770_set_uvd_clocks()
72 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
87 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
118 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/rga/
H A Drga_reg_info.h20 #define ABS(X) (((X) < 0) ? (-(X)) : (X))
106 #define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 )
108 #define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 )
109 #define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 )
110 #define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 )
114 #define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 )
117 #define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 )
119 #define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 )
120 #define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 )
121 #define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 )
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igbvf/
H A Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
10 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
11 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
12 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
13 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
14 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
16 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra20.c12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos54xx.dtsi47 reg = <0x12D10000 0x100>;
48 interrupts = <0 106 0>;
54 #size-cells = <0>;
56 reg = <0x12CA0000 0x100>;
57 interrupts = <0 60 0>;
62 #size-cells = <0>;
64 reg = <0x12CB0000 0x100>;
65 interrupts = <0 61 0>;
70 #size-cells = <0>;
72 reg = <0x12CC0000 0x100>;
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dwm8770.c37 { 0, 0x7f },
38 { 1, 0x7f },
39 { 2, 0x7f },
40 { 3, 0x7f },
41 { 4, 0x7f },
42 { 5, 0x7f },
43 { 6, 0x7f },
44 { 7, 0x7f },
45 { 8, 0x7f },
46 { 9, 0xff },
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos5.dtsi40 reg = <0x10000000 0x100>;
45 reg = <0x12250000 0x14>;
53 reg = <0x10440000 0x1000>;
54 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x2000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
102 reg = <0x10050000 0x5000>;
107 reg = <0x12C00000 0x100>;
[all …]
H A Dtango4-common.dtsi9 #define CPU_CLK 0
24 #clock-cells = <0>;
29 ranges = <0x00000000 0x20000000 0x2000>;
33 scu@0 {
35 reg = <0x0 0x100>;
40 reg = <0x600 0x10>;
50 reg = <0x1000 0x1000>, <0x100 0x100>;
56 reg = <0x20100000 0x1000>;
71 #clock-cells = <0>;
76 reg = <0x10000 0x100>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x2000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ralink/
H A Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/
H A Dst_smi.c49 FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
50 FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
51 FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
52 FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
53 FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
54 FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
55 FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
56 FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
57 FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
58 FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
[all …]
/OK3568_Linux_fs/buildroot/dl/unixbench/git/UnixBench/pgms/
H A Dgfx-x1148 'rect100' => [ 110000.0, "100x100 rectangle" ],
52 'srect100' => [ 110000.0, "100x100 stippled rectangle (8x8 stipple)" ],
56 'osrect100' => [ 110000.0, "100x100 opaque stippled rectangle (8x8 stipple)" ],
60 'tilerect100' => [ 110000.0, "100x100 tiled rectangle (4x4 tile)" ],
64 'oddsrect100' => [ 55600.0, "100x100 stippled rectangle (17x15 stipple)" ],
68 'oddosrect100' => [ 54500.0, "100x100 opaque stippled rectangle (17x15 stipple)" ],
72 'oddtilerect100' => [ 54500.0, "100x100 tiled rectangle (17x15 tile)" ],
76 'bigsrect100' => [ 12300.0, "100x100 stippled rectangle (161x145 stipple)" ],
80 'bigosrect100' => [ 12800.0, "100x100 opaque stippled rectangle (161x145 stipple)" ],
84 'bigtilerect100' => [ 16200.0, "100x100 tiled rectangle (161x145 tile)" ],
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi11 reg = <0x00 0x70000000 0x00 0x100000>;
14 ranges = <0x00 0x00 0x70000000 0x100000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
23 reg = <0x00 0x00100000 0x00 0x1c000>;
26 ranges = <0x00 0x00 0x00100000 0x1c000>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi21 service_reserved: svcbuffer@0 {
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
31 #size-cells = <0>;
33 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x1>;
51 reg = <0x2>;
58 reg = <0x3>;
64 interrupts = <0 170 4>,
[all …]
/OK3568_Linux_fs/kernel/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c112 TEST_REG = 0,
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in igb_get_link_ksettings()
257 return 0; in igb_get_link_ksettings()
338 /* fix up the value for auto (3 => 0) as zero is mapped in igb_set_link_ksettings()
355 return 0; in igb_set_link_ksettings()
399 int retval = 0; in igb_set_pauseparam()
435 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_pauseparam()
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); in igb_get_regs()
[all …]

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