1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __REG_INFO_H__ 3*4882a593Smuzhiyun #define __REG_INFO_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun //#include "chip_register.h" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun //#include "rga_struct.h" 9*4882a593Smuzhiyun #include "rga.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef MIN 12*4882a593Smuzhiyun #define MIN(X, Y) ((X)<(Y)?(X):(Y)) 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef MAX 16*4882a593Smuzhiyun #define MAX(X, Y) ((X)>(Y)?(X):(Y)) 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef ABS 20*4882a593Smuzhiyun #define ABS(X) (((X) < 0) ? (-(X)) : (X)) 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef CLIP 24*4882a593Smuzhiyun #define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x)) 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun //RGA register map 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun //General Registers 30*4882a593Smuzhiyun #define rRGA_SYS_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_SYS_CTRL)) 31*4882a593Smuzhiyun #define rRGA_CMD_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_CTRL)) 32*4882a593Smuzhiyun #define rRGA_CMD_ADDR (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_ADDR)) 33*4882a593Smuzhiyun #define rRGA_STATUS (*(volatile uint32_t *)(RGA_BASE + RGA_STATUS)) 34*4882a593Smuzhiyun #define rRGA_INT (*(volatile uint32_t *)(RGA_BASE + RGA_INT)) 35*4882a593Smuzhiyun #define rRGA_AXI_ID (*(volatile uint32_t *)(RGA_BASE + RGA_AXI_ID)) 36*4882a593Smuzhiyun #define rRGA_MMU_STA_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA_CTRL)) 37*4882a593Smuzhiyun #define rRGA_MMU_STA (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA)) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun //Command code start 40*4882a593Smuzhiyun #define rRGA_MODE_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MODE_CTRL)) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun //Source Image Registers 43*4882a593Smuzhiyun #define rRGA_SRC_Y_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_MST)) 44*4882a593Smuzhiyun #define rRGA_SRC_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CB_MST)) 45*4882a593Smuzhiyun #define rRGA_MASK_READ_MST (*(volatile uint32_t *)(RGA_BASE + RGA_MASK_READ_MST)) //repeat 46*4882a593Smuzhiyun #define rRGA_SRC_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CR_MST)) 47*4882a593Smuzhiyun #define rRGA_SRC_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_VIR_INFO)) 48*4882a593Smuzhiyun #define rRGA_SRC_ACT_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_ACT_INFO)) 49*4882a593Smuzhiyun #define rRGA_SRC_X_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_X_PARA)) 50*4882a593Smuzhiyun #define rRGA_SRC_Y_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_PARA)) 51*4882a593Smuzhiyun #define rRGA_SRC_TILE_XINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_XINFO)) 52*4882a593Smuzhiyun #define rRGA_SRC_TILE_YINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_YINFO)) 53*4882a593Smuzhiyun #define rRGA_SRC_TILE_H_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_H_INCR)) 54*4882a593Smuzhiyun #define rRGA_SRC_TILE_V_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_V_INCR)) 55*4882a593Smuzhiyun #define rRGA_SRC_TILE_OFFSETX (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETX)) 56*4882a593Smuzhiyun #define rRGA_SRC_TILE_OFFSETY (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETY)) 57*4882a593Smuzhiyun #define rRGA_SRC_BG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_BG_COLOR)) 58*4882a593Smuzhiyun #define rRGA_SRC_FG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_FG_COLOR)) 59*4882a593Smuzhiyun #define rRGA_LINE_DRAWING_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_COLOR)) //repeat 60*4882a593Smuzhiyun #define rRGA_SRC_TR_COLOR0 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR0)) 61*4882a593Smuzhiyun #define rRGA_CP_GR_A (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_A)) //repeat 62*4882a593Smuzhiyun #define rRGA_SRC_TR_COLOR1 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR1)) 63*4882a593Smuzhiyun #define rRGA_CP_GR_B (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_B)) //repeat 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define rRGA_LINE_DRAW (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW)) 66*4882a593Smuzhiyun #define rRGA_PAT_START_POINT (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_START_POINT)) //repeat 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun //Destination Image Registers 69*4882a593Smuzhiyun #define rRGA_DST_MST (*(volatile uint32_t *)(RGA_BASE + RGA_DST_MST)) 70*4882a593Smuzhiyun #define rRGA_LUT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LUT_MST)) //repeat 71*4882a593Smuzhiyun #define rRGA_PAT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_MST)) //repeat 72*4882a593Smuzhiyun #define rRGA_LINE_DRAWING_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_MST)) //repeat 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define rRGA_DST_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO)) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define rRGA_DST_CTR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO)) 77*4882a593Smuzhiyun #define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun //Alpha/ROP Registers 80*4882a593Smuzhiyun #define rRGA_ALPHA_CON (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON)) 81*4882a593Smuzhiyun #define rRGA_FADING_CON (*(volatile uint32_t *)(RGA_BASE + RGA_FADING_CON)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define rRGA_PAT_CON (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_CON)) 84*4882a593Smuzhiyun #define rRGA_DST_VIR_WIDTH_PIX (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX)) //repeat 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define rRGA_ROP_CON0 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON0)) 87*4882a593Smuzhiyun #define rRGA_CP_GR_G (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_G)) //repeat 88*4882a593Smuzhiyun #define rRGA_PRESCL_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CB_MST)) //repeat 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define rRGA_ROP_CON1 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON1)) 91*4882a593Smuzhiyun #define rRGA_CP_GR_R (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_R)) //repeat 92*4882a593Smuzhiyun #define rRGA_PRESCL_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CR_MST)) //repeat 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun //MMU Register 95*4882a593Smuzhiyun #define rRGA_MMU_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_CTRL)) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun //----------------------------------------------------------------- 101*4882a593Smuzhiyun //reg detail definition 102*4882a593Smuzhiyun //----------------------------------------------------------------- 103*4882a593Smuzhiyun /*RGA_SYS_CTRL*/ 104*4882a593Smuzhiyun #define m_RGA_SYS_CTRL_CMD_MODE ( 1<<2 ) 105*4882a593Smuzhiyun #define m_RGA_SYS_CTRL_OP_ST_SLV ( 1<<1 ) 106*4882a593Smuzhiyun #define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 ) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 ) 109*4882a593Smuzhiyun #define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 ) 110*4882a593Smuzhiyun #define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 ) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /*RGA_CMD_CTRL*/ 114*4882a593Smuzhiyun #define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 ) 115*4882a593Smuzhiyun #define m_RGA_CMD_CTRL_CMD_STOP_MODE ( 1<<2 ) 116*4882a593Smuzhiyun #define m_RGA_CMD_CTRL_CMD_INCR_VALID ( 1<<1 ) 117*4882a593Smuzhiyun #define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 ) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 ) 120*4882a593Smuzhiyun #define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 ) 121*4882a593Smuzhiyun #define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 ) 122*4882a593Smuzhiyun #define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x) ( (x*0x1)<<0 ) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /*RGA_STATUS*/ 126*4882a593Smuzhiyun #define m_RGA_CMD_STATUS_CMD_TOTAL_NUM ( 0xfff<<20 ) 127*4882a593Smuzhiyun #define m_RGA_CMD_STATUS_NOW_CMD_NUM ( 0xfff<<8 ) 128*4882a593Smuzhiyun #define m_RGA_CMD_STATUS_ENGINE_STATUS ( 1<<0 ) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /*RGA_INT*/ 132*4882a593Smuzhiyun #define m_RGA_INT_ALL_CMD_DONE_INT_EN ( 1<<10 ) 133*4882a593Smuzhiyun #define m_RGA_INT_MMU_INT_EN ( 1<<9 ) 134*4882a593Smuzhiyun #define m_RGA_INT_ERROR_INT_EN ( 1<<8 ) 135*4882a593Smuzhiyun #define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 ) 136*4882a593Smuzhiyun #define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 ) 137*4882a593Smuzhiyun #define m_RGA_INT_MMU_INT_CLEAR ( 1<<5 ) 138*4882a593Smuzhiyun #define m_RGA_INT_ERROR_INT_CLEAR ( 1<<4 ) 139*4882a593Smuzhiyun #define m_RGA_INT_NOW_CMD_DONE_INT_FLAG ( 1<<3 ) 140*4882a593Smuzhiyun #define m_RGA_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 ) 141*4882a593Smuzhiyun #define m_RGA_INT_MMU_INT_FLAG ( 1<<1 ) 142*4882a593Smuzhiyun #define m_RGA_INT_ERROR_INT_FLAG ( 1<<0 ) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define s_RGA_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 ) 145*4882a593Smuzhiyun #define s_RGA_INT_MMU_INT_EN(x) ( (x&0x1)<<9 ) 146*4882a593Smuzhiyun #define s_RGA_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 ) 147*4882a593Smuzhiyun #define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 ) 148*4882a593Smuzhiyun #define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 ) 149*4882a593Smuzhiyun #define s_RGA_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 ) 150*4882a593Smuzhiyun #define s_RGA_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 ) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /*RGA_AXI_ID*/ 154*4882a593Smuzhiyun #define m_RGA_AXI_ID_MMU_READ ( 3<<30 ) 155*4882a593Smuzhiyun #define m_RGA_AXI_ID_MMU_WRITE ( 3<<28 ) 156*4882a593Smuzhiyun #define m_RGA_AXI_ID_MASK_READ ( 0xf<<24 ) 157*4882a593Smuzhiyun #define m_RGA_AXI_ID_CMD_FET ( 0xf<<20 ) 158*4882a593Smuzhiyun #define m_RGA_AXI_ID_DST_WRITE ( 0xf<<16 ) 159*4882a593Smuzhiyun #define m_RGA_AXI_ID_DST_READ ( 0xf<<12 ) 160*4882a593Smuzhiyun #define m_RGA_AXI_ID_SRC_CR_READ ( 0xf<<8 ) 161*4882a593Smuzhiyun #define m_RGA_AXI_ID_SRC_CB_READ ( 0xf<<4 ) 162*4882a593Smuzhiyun #define m_RGA_AXI_ID_SRC_Y_READ ( 0xf<<0 ) 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define s_RGA_AXI_ID_MMU_READ(x) ( (x&0x3)<<30 ) 165*4882a593Smuzhiyun #define s_RGA_AXI_ID_MMU_WRITE(x) ( (x&0x3)<<28 ) 166*4882a593Smuzhiyun #define s_RGA_AXI_ID_MASK_READ(x) ( (x&0xf)<<24 ) 167*4882a593Smuzhiyun #define s_RGA_AXI_ID_CMD_FET(x) ( (x&0xf)<<20 ) 168*4882a593Smuzhiyun #define s_RGA_AXI_ID_DST_WRITE(x) ( (x&0xf)<<16 ) 169*4882a593Smuzhiyun #define s_RGA_AXI_ID_DST_READ(x) ( (x&0xf)<<12 ) 170*4882a593Smuzhiyun #define s_RGA_AXI_ID_SRC_CR_READ(x) ( (x&0xf)<<8 ) 171*4882a593Smuzhiyun #define s_RGA_AXI_ID_SRC_CB_READ(x) ( (x&0xf)<<4 ) 172*4882a593Smuzhiyun #define s_RGA_AXI_ID_SRC_Y_READ(x) ( (x&0xf)<<0 ) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /*RGA_MMU_STA_CTRL*/ 176*4882a593Smuzhiyun #define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR ( 1<<3 ) 177*4882a593Smuzhiyun #define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME ( 1<<2 ) 178*4882a593Smuzhiyun #define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE ( 1<<1 ) 179*4882a593Smuzhiyun #define m_RGA_MMU_STA_CTRL_TLB_STA_EN ( 1<<0 ) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x) ( (x&0x1)<<3 ) 182*4882a593Smuzhiyun #define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x) ( (x&0x1)<<2 ) 183*4882a593Smuzhiyun #define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x) ( (x&0x1)<<1 ) 184*4882a593Smuzhiyun #define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x) ( (x&0x1)<<0 ) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* RGA_MODE_CTRL */ 189*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_2D_RENDER_MODE ( 7<<0 ) 190*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_RGB_PACK ( 1<<3 ) 191*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_FORMAT ( 15<<4 ) 192*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_RB_SWAP ( 1<<8 ) 193*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP ( 1<<9 ) 194*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE ( 1<<10 ) 195*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE ( 3<<11 ) 196*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TRANS_MODE (0x1f<<13 ) 197*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TR_MODE ( 1<<13 ) 198*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TR_R_EN ( 1<<14 ) 199*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TR_G_EN ( 1<<15 ) 200*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TR_B_EN ( 1<<16 ) 201*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SRC_TR_A_EN ( 1<<17 ) 202*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_ROTATE_MODE ( 3<<18 ) 203*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_SCALE_MODE ( 3<<20 ) 204*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_PAT_SEL ( 1<<22 ) 205*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_DST_FORMAT ( 3<<23 ) 206*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_DST_RGB_PACK ( 1<<25 ) 207*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_DST_RB_SWAP ( 1<<26 ) 208*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_DST_ALPHA_SWAP ( 1<<27 ) 209*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE ( 1<<28 ) 210*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_CMD_INT_ENABLE ( 1<<29 ) 211*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE ( 1<<30 ) 212*4882a593Smuzhiyun #define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE ( 1<<30 ) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_2D_RENDER_MODE(x) ( (x&0x7)<<0 ) 217*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_RGB_PACK(x) ( (x&0x1)<<3 ) 218*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_FORMAT(x) ( (x&0xf)<<4 ) 219*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_RB_SWAP(x) ( (x&0x1)<<8 ) 220*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x) ( (x&0x1)<<9 ) 221*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x) ( (x&0x1)<<10 ) 222*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x) ( (x&0x3)<<11 ) 223*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x) ( (x&0x1f)<<13 ) 224*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TR_MODE(x) ( (x&0x1)<<13 ) 225*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TR_R_EN(x) ( (x&0x1)<<14 ) 226*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TR_G_EN(x) ( (x&0x1)<<15 ) 227*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TR_B_EN(x) ( (x&0x1)<<16 ) 228*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SRC_TR_A_EN(x) ( (x&0x1)<<17 ) 229*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_ROTATE_MODE(x) ( (x&0x3)<<18 ) 230*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_SCALE_MODE(x) ( (x&0x3)<<20 ) 231*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_PAT_SEL(x) ( (x&0x1)<<22 ) 232*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_DST_FORMAT(x) ( (x&0x3)<<23 ) 233*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_DST_RGB_PACK(x) ( (x&0x1)<<25 ) 234*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_DST_RB_SWAP(x) ( (x&0x1)<<26 ) 235*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x) ( (x&0x1)<<27 ) 236*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x) ( (x&0x1)<<28 ) 237*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x) ( (x&0x1)<<29 ) 238*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x) ( (x&0x1)<<30 ) 239*4882a593Smuzhiyun #define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x) ( (x&0x1)<<31 ) 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* RGA_LINE_DRAW */ 244*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_MAJOR_WIDTH ( 0x7ff<<0 ) 245*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_LINE_DIRECTION ( 0x1<<11) 246*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_LINE_WIDTH ( 0xf<<12) 247*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_INCR_VALUE ( 0xfff<<16) 248*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_DIR_MAJOR ( 0x1<<28) 249*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR ( 0x1<<29) 250*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_LAST_POINT ( 0x1<<30) 251*4882a593Smuzhiyun #define m_RGA_LINE_DRAW_ANTI_ALISING ( 0x1<<31) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_MAJOR_WIDTH(x) (((x)&0x7ff)<<0 ) 254*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_LINE_DIRECTION(x) ( ((x)&0x1)<<11) 255*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_LINE_WIDTH(x) ( ((x)&0xf)<<12) 256*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_INCR_VALUE(x) (((x)&0xfff)<<16) 257*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_DIR_MAJOR(x) ( ((x)&0x1)<<28) 258*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x) ( ((x)&0x1)<<29) 259*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30) 260*4882a593Smuzhiyun #define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* RGA_ALPHA_CON */ 264*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 ) 265*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 ) 266*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_ALPHA_MODE ( 0x3<<2 ) 267*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_PD_MODE ( 0xf<<4 ) 268*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE (0xff<<8 ) 269*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_PD_M_SEL ( 0x1<<16) 270*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_FADING_ENABLE ( 0x1<<17) 271*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_ROP_MODE_SEL ( 0x3<<18) 272*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_CAL_MODE_SEL ( 0x1<<28) 273*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_DITHER_ENABLE ( 0x1<<29) 274*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE ( 0x1<<30) 275*4882a593Smuzhiyun #define m_RGA_ALPHA_CON_AA_SEL ( 0x1<<31) 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_ENABLE(x) ( (x&0x1)<<0 ) 278*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_A_OR_R_SEL(x) ( (x&0x1)<<1 ) 279*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_ALPHA_MODE(x) ( (x&0x3)<<2 ) 280*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_PD_MODE(x) ( (x&0xf)<<4 ) 281*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x) ((x&0xff)<<8 ) 282*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_PD_M_SEL(x) ( (x&0x1)<<16) 283*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_FADING_ENABLE(x) ( (x&0x1)<<17) 284*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_ROP_MODE_SEL(x) ( (x&0x3)<<18) 285*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_CAL_MODE_SEL(x) ( (x&0x1)<<28) 286*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_DITHER_ENABLE(x) ( (x&0x1)<<29) 287*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x) ( (x&0x1)<<30) 288*4882a593Smuzhiyun #define s_RGA_ALPHA_CON_AA_SEL(x) ( (x&0x1)<<31) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* blur sharp mode */ 292*4882a593Smuzhiyun #define m_RGA_BLUR_SHARP_FILTER_MODE ( 0x1<<25 ) 293*4882a593Smuzhiyun #define m_RGA_BLUR_SHARP_FILTER_TYPE ( 0x3<<26 ) 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun #define s_RGA_BLUR_SHARP_FILTER_MODE(x) ( (x&0x1)<<25 ) 296*4882a593Smuzhiyun #define s_RGA_BLUR_SHARP_FILTER_TYPE(x) ( (x&0x3)<<26 ) 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* pre scale mode */ 300*4882a593Smuzhiyun #define m_RGA_PRE_SCALE_HOR_RATIO ( 0x3 <<20 ) 301*4882a593Smuzhiyun #define m_RGA_PRE_SCALE_VER_RATIO ( 0x3 <<22 ) 302*4882a593Smuzhiyun #define m_RGA_PRE_SCALE_OUTPUT_FORMAT ( 0x1 <<24 ) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define s_RGA_PRE_SCALE_HOR_RATIO(x) ( (x&0x3) <<20 ) 305*4882a593Smuzhiyun #define s_RGA_PRE_SCALE_VER_RATIO(x) ( (x&0x3) <<22 ) 306*4882a593Smuzhiyun #define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x) ( (x&0x1) <<24 ) 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* RGA_MMU_CTRL*/ 311*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_TLB_ADDR ( 0xffffffff<<0) 312*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE ( 0x3<<4 ) 313*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_MMU_ENABLE ( 0x1<<0 ) 314*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_SRC_FLUSH ( 0x1<<1 ) 315*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_DST_FLUSH ( 0x1<<2 ) 316*4882a593Smuzhiyun #define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH ( 0x1<<3 ) 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_TLB_ADDR(x) ((x&0xffffffff)) 319*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x) ((x&0x3)<<4) 320*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_MMU_ENABLE(x) ((x&0x1)<<0) 321*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_SRC_FLUSH(x) ((x&0x1)<<1) 322*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_DST_FLUSH(x) ((x&0x1)<<2) 323*4882a593Smuzhiyun #define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x) ((x&0x1)<<3) 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #endif 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* 328*4882a593Smuzhiyun #define RGA_MODE_CTRL_OFFSET 0x0 329*4882a593Smuzhiyun #define RGA_SRC_Y_MST_OFFSET 0x4 330*4882a593Smuzhiyun #define RGA_SRC_CB_MST_OFFSET 0x8 331*4882a593Smuzhiyun #define RGA_SRC_CR_MST_OFFSET 0xc 332*4882a593Smuzhiyun #define RGA_SRC_VIR_INFO_OFFSET 0x10 333*4882a593Smuzhiyun #define RGA_SRC_ACT_INFO_OFFSET 0x14 334*4882a593Smuzhiyun #define RGA_SRC_X_PARA_OFFSET 0x18 335*4882a593Smuzhiyun #define RGA_SRC_Y_PARA_OFFSET 0x1c 336*4882a593Smuzhiyun #define RGA_SRC_TILE_XINFO_OFFSET 0x20 337*4882a593Smuzhiyun #define RGA_SRC_TILE_YINFO_OFFSET 0x24 338*4882a593Smuzhiyun #define RGA_SRC_TILE_H_INCR_OFFSET 0x28 339*4882a593Smuzhiyun #define RGA_SRC_TILE_V_INCR_OFFSET 0x2c 340*4882a593Smuzhiyun #define RGA_SRC_TILE_OFFSETX_OFFSET 0x30 341*4882a593Smuzhiyun #define RGA_SRC_TILE_OFFSETY_OFFSET 0x34 342*4882a593Smuzhiyun #define RGA_SRC_BG_COLOR_OFFSET 0x38 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define RGA_SRC_FG_COLOR_OFFSET 0x3c 345*4882a593Smuzhiyun #define RGA_LINE_DRAWING_COLOR_OFFSET 0x3c 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun #define RGA_SRC_TR_COLOR0_OFFSET 0x40 348*4882a593Smuzhiyun #define RGA_CP_GR_A_OFFSET 0x40 //repeat 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun #define RGA_SRC_TR_COLOR1_OFFSET 0x44 351*4882a593Smuzhiyun #define RGA_CP_GR_B_OFFSET 0x44 //repeat 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define RGA_LINE_DRAW_OFFSET 0x48 354*4882a593Smuzhiyun #define RGA_PAT_START_POINT_OFFSET 0x48 //repeat 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define RGA_DST_MST_OFFSET 0x4c 357*4882a593Smuzhiyun #define RGA_LUT_MST_OFFSET 0x4c //repeat 358*4882a593Smuzhiyun #define RGA_PAT_MST_OFFSET 0x4c //repeat 359*4882a593Smuzhiyun #define RGA_LINE_DRAWING_MST_OFFSET 0x4c //repeat 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun #define RGA_DST_VIR_INFO_OFFSET 0x50 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define RGA_DST_CTR_INFO_OFFSET 0x54 364*4882a593Smuzhiyun #define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun #define RGA_ALPHA_CON_OFFSET 0x58 367*4882a593Smuzhiyun #define RGA_FADING_CON_OFFSET 0x5c 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define RGA_PAT_CON_OFFSET 0x60 370*4882a593Smuzhiyun #define RGA_LINE_DRAWING_WIDTH_OFFSET 0x60 //repeat 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #define RGA_ROP_CON0_OFFSET 0x64 373*4882a593Smuzhiyun #define RGA_CP_GR_G_OFFSET 0x64 //repeat 374*4882a593Smuzhiyun #define RGA_PRESCL_CB_MST_OFFSET 0x64 //repeat 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun #define RGA_ROP_CON1_OFFSET 0x68 377*4882a593Smuzhiyun #define RGA_CP_GR_R_OFFSET 0x68 //repeat 378*4882a593Smuzhiyun #define RGA_PRESCL_CR_MST_OFFSET 0x68 //repeat 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define RGA_MMU_CTRL_OFFSET 0x6c 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun #define RGA_SYS_CTRL_OFFSET 0x000 384*4882a593Smuzhiyun #define RGA_CMD_CTRL_OFFSET 0x004 385*4882a593Smuzhiyun #define RGA_CMD_ADDR_OFFSET 0x008 386*4882a593Smuzhiyun #define RGA_STATUS_OFFSET 0x00c 387*4882a593Smuzhiyun #define RGA_INT_OFFSET 0x010 388*4882a593Smuzhiyun #define RGA_AXI_ID_OFFSET 0x014 389*4882a593Smuzhiyun #define RGA_MMU_STA_CTRL_OFFSET 0x018 390*4882a593Smuzhiyun #define RGA_MMU_STA_OFFSET 0x01c 391*4882a593Smuzhiyun */ 392*4882a593Smuzhiyun //hxx 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun #define RGA_SYS_CTRL_OFFSET (RGA_SYS_CTRL-0x100) 395*4882a593Smuzhiyun #define RGA_CMD_CTRL_OFFSET (RGA_CMD_CTRL-0x100) 396*4882a593Smuzhiyun #define RGA_CMD_ADDR_OFFSET (RGA_CMD_ADDR-0x100) 397*4882a593Smuzhiyun #define RGA_STATUS_OFFSET (RGA_STATUS-0x100) 398*4882a593Smuzhiyun #define RGA_INT_OFFSET (RGA_INT-0x100) 399*4882a593Smuzhiyun #define RGA_AXI_ID_OFFSET (RGA_AXI_ID-0x100) 400*4882a593Smuzhiyun #define RGA_MMU_STA_CTRL_OFFSET (RGA_MMU_STA_CTRL-0x100) 401*4882a593Smuzhiyun #define RGA_MMU_STA_OFFSET (RGA_MMU_STA-0x100) 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #define RGA_MODE_CTRL_OFFSET (RGA_MODE_CTRL-0x100) 404*4882a593Smuzhiyun #define RGA_SRC_Y_MST_OFFSET (RGA_SRC_Y_MST-0x100) 405*4882a593Smuzhiyun #define RGA_SRC_CB_MST_OFFSET (RGA_SRC_CB_MST-0x100) 406*4882a593Smuzhiyun #define RGA_SRC_CR_MST_OFFSET (RGA_SRC_CR_MST-0x100) 407*4882a593Smuzhiyun #define RGA_SRC_VIR_INFO_OFFSET (RGA_SRC_VIR_INFO-0x100) 408*4882a593Smuzhiyun #define RGA_SRC_ACT_INFO_OFFSET (RGA_SRC_ACT_INFO-0x100) 409*4882a593Smuzhiyun #define RGA_SRC_X_PARA_OFFSET (RGA_SRC_X_PARA-0x100) 410*4882a593Smuzhiyun #define RGA_SRC_Y_PARA_OFFSET (RGA_SRC_Y_PARA-0x100) 411*4882a593Smuzhiyun #define RGA_SRC_TILE_XINFO_OFFSET (RGA_SRC_TILE_XINFO-0x100) 412*4882a593Smuzhiyun #define RGA_SRC_TILE_YINFO_OFFSET (RGA_SRC_TILE_YINFO-0x100) 413*4882a593Smuzhiyun #define RGA_SRC_TILE_H_INCR_OFFSET (RGA_SRC_TILE_H_INCR-0x100) 414*4882a593Smuzhiyun #define RGA_SRC_TILE_V_INCR_OFFSET (RGA_SRC_TILE_V_INCR-0x100) 415*4882a593Smuzhiyun #define RGA_SRC_TILE_OFFSETX_OFFSET (RGA_SRC_TILE_OFFSETX-0x100) 416*4882a593Smuzhiyun #define RGA_SRC_TILE_OFFSETY_OFFSET (RGA_SRC_TILE_OFFSETY-0x100) 417*4882a593Smuzhiyun #define RGA_SRC_BG_COLOR_OFFSET (RGA_SRC_BG_COLOR-0x100) 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun #define RGA_SRC_FG_COLOR_OFFSET (RGA_SRC_FG_COLOR-0x100) 420*4882a593Smuzhiyun #define RGA_LINE_DRAWING_COLOR_OFFSET (RGA_LINE_DRAWING_COLOR-0x100) 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun #define RGA_SRC_TR_COLOR0_OFFSET (RGA_SRC_TR_COLOR0-0x100) 423*4882a593Smuzhiyun #define RGA_CP_GR_A_OFFSET (RGA_CP_GR_A-0x100) //repeat 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun #define RGA_SRC_TR_COLOR1_OFFSET (RGA_SRC_TR_COLOR1-0x100) 426*4882a593Smuzhiyun #define RGA_CP_GR_B_OFFSET (RGA_CP_GR_B-0x100) //repeat 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #define RGA_LINE_DRAW_OFFSET (RGA_LINE_DRAW-0x100) 429*4882a593Smuzhiyun #define RGA_PAT_START_POINT_OFFSET (RGA_PAT_START_POINT-0x100) //repeat 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define RGA_DST_MST_OFFSET (RGA_DST_MST-0x100) 432*4882a593Smuzhiyun #define RGA_LUT_MST_OFFSET (RGA_LUT_MST-0x100) //repeat 433*4882a593Smuzhiyun #define RGA_PAT_MST_OFFSET (RGA_PAT_MST-0x100) //repeat 434*4882a593Smuzhiyun #define RGA_LINE_DRAWING_MST_OFFSET (RGA_LINE_DRAWING_MST-0x100) //repeat 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun #define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100) 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun #define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100) 439*4882a593Smuzhiyun #define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun #define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100) 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun #define RGA_PAT_CON_OFFSET (RGA_PAT_CON-0x100) 444*4882a593Smuzhiyun #define RGA_LINE_DRAWING_WIDTH_OFFSET (RGA_DST_VIR_WIDTH_PIX-0x100) //repeat 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define RGA_ROP_CON0_OFFSET (RGA_ROP_CON0-0x100) 447*4882a593Smuzhiyun #define RGA_CP_GR_G_OFFSET (RGA_CP_GR_G-0x100) //repeat 448*4882a593Smuzhiyun #define RGA_PRESCL_CB_MST_OFFSET (RGA_PRESCL_CB_MST-0x100) //repeat 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #define RGA_ROP_CON1_OFFSET (RGA_ROP_CON1-0x100) 451*4882a593Smuzhiyun #define RGA_CP_GR_R_OFFSET (RGA_CP_GR_R-0x100) //repeat 452*4882a593Smuzhiyun #define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun #define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100) 455*4882a593Smuzhiyun #define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100) 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun #define RGA_YUV_OUT_CFG_OFFSET (RGA_YUV_OUT_CFG-0x100) 458*4882a593Smuzhiyun #define RGA_DST_UV_MST_OFFSET (RGA_DST_UV_MST-0x100) 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun void matrix_cal(const struct rga_req *msg, TILE_INFO *tile); 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base); 466*4882a593Smuzhiyun uint8_t RGA_pixel_width_init(uint32_t format); 467*4882a593Smuzhiyun 468