Searched +full:0 +full:x01c0e000 (Results 1 – 11 of 11) sorted by relevance
77 reg = <0x01c0e000 0x1000>;
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
11 #size-cells = <0>;13 cpu0: cpu@0 {16 reg = <0>;84 reg = <0x01c00000 0x1000>;91 reg = <0x00018000 0x1c000>;94 ranges = <0 0x00018000 0x1c000>;96 ve_sram: sram-section@0 {99 reg = <0x000000 0x1c000>;106 reg = <0x01c0e000 0x1000>;117 reg = <0x01c15000 0x1000>;[all …]
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;71 #clock-cells = <0>;113 reg = <0x1000000 0x400000>;117 ranges = <0 0x1000000 0x400000>;119 display_clocks: clock@0 {121 reg = <0x0 0x10000>;132 compatible = "allwinner,sun50i-h6-de3-mixer-0";133 reg = <0x100000 0x100000>;[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]
72 #size-cells = <0>;74 cpu0: cpu@0 {77 reg = <0>;155 reg = <0x01400000 0x20000>;168 reg = <0x01c00000 0x1000>;175 reg = <0x01d00000 0x80000>;178 ranges = <0 0x01d00000 0x80000>;180 ve_sram: sram-section@0 {183 reg = <0x000000 0x80000>;190 reg = <0x01c0e000 0x1000>;[all …]
127 cpu@0 {208 reg = <0x01c0e000 0x1000>;219 reg = <0x01c15000 0x1000>;228 #sound-dai-cells = <0>;230 reg = <0x01c22c00 0x200>;241 #sound-dai-cells = <0>;243 reg = <0x01c22e00 0x400>;252 reg = <0x01c25000 0x100>;253 #thermal-sensor-cells = <0>;254 #io-channel-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]