1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Video Engine Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  compatible:
15*4882a593Smuzhiyun    enum:
16*4882a593Smuzhiyun      - allwinner,sun4i-a10-video-engine
17*4882a593Smuzhiyun      - allwinner,sun5i-a13-video-engine
18*4882a593Smuzhiyun      - allwinner,sun7i-a20-video-engine
19*4882a593Smuzhiyun      - allwinner,sun8i-a33-video-engine
20*4882a593Smuzhiyun      - allwinner,sun8i-h3-video-engine
21*4882a593Smuzhiyun      - allwinner,sun50i-a64-video-engine
22*4882a593Smuzhiyun      - allwinner,sun50i-h5-video-engine
23*4882a593Smuzhiyun      - allwinner,sun50i-h6-video-engine
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  reg:
26*4882a593Smuzhiyun    maxItems: 1
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  interrupts:
29*4882a593Smuzhiyun    maxItems: 1
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  clocks:
32*4882a593Smuzhiyun    items:
33*4882a593Smuzhiyun      - description: Bus Clock
34*4882a593Smuzhiyun      - description: Module Clock
35*4882a593Smuzhiyun      - description: RAM Clock
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  clock-names:
38*4882a593Smuzhiyun    items:
39*4882a593Smuzhiyun      - const: ahb
40*4882a593Smuzhiyun      - const: mod
41*4882a593Smuzhiyun      - const: ram
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun  resets:
44*4882a593Smuzhiyun    maxItems: 1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  allwinner,sram:
47*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle-array
48*4882a593Smuzhiyun    description: Phandle to the device SRAM
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  iommus:
51*4882a593Smuzhiyun    maxItems: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  memory-region:
54*4882a593Smuzhiyun    description:
55*4882a593Smuzhiyun      CMA pool to use for buffers allocation instead of the default
56*4882a593Smuzhiyun      CMA pool.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyunrequired:
59*4882a593Smuzhiyun  - compatible
60*4882a593Smuzhiyun  - reg
61*4882a593Smuzhiyun  - interrupts
62*4882a593Smuzhiyun  - clocks
63*4882a593Smuzhiyun  - clock-names
64*4882a593Smuzhiyun  - resets
65*4882a593Smuzhiyun  - allwinner,sram
66*4882a593Smuzhiyun
67*4882a593SmuzhiyunadditionalProperties: false
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunexamples:
70*4882a593Smuzhiyun  - |
71*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
72*4882a593Smuzhiyun    #include <dt-bindings/clock/sun7i-a20-ccu.h>
73*4882a593Smuzhiyun    #include <dt-bindings/reset/sun4i-a10-ccu.h>
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun    video-codec@1c0e000 {
76*4882a593Smuzhiyun        compatible = "allwinner,sun7i-a20-video-engine";
77*4882a593Smuzhiyun        reg = <0x01c0e000 0x1000>;
78*4882a593Smuzhiyun        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
79*4882a593Smuzhiyun        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
80*4882a593Smuzhiyun                 <&ccu CLK_DRAM_VE>;
81*4882a593Smuzhiyun        clock-names = "ahb", "mod", "ram";
82*4882a593Smuzhiyun        resets = <&ccu RST_VE>;
83*4882a593Smuzhiyun        allwinner,sram = <&ve_sram 1>;
84*4882a593Smuzhiyun    };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun...
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