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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx28-m28cu3.dts15 reg = <0x40000000 0x08000000>;
24 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
27 partition@0 {
28 label = "gpmi-nfc-0-boot";
29 reg = <0x00000000 0x01400000>;
35 reg = <0x01400000 0x0ec00000>;
42 pinctrl-0 = <&mmc0_4bit_pins_a
53 pinctrl-0 = <&mmc2_4bit_pins_a
63 pinctrl-0 = <&hog_pins_a>;
65 hog_pins_a: hog@0 {
[all …]
H A Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dallwinner,sun8i-h3-deinterlace.yaml69 reg = <0x01400000 0x20000>;
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A Dof.c17 #define PROG_START 0x01400000 /* only used on 64-bit systems */
19 #define ONE_MB 0x100000
30 unsigned long addr = 0; in of_try_claim()
32 if (claim_base == 0) in of_try_claim()
37 printf(" trying: 0x%08lx\n\r", claim_base); in of_try_claim()
39 addr = (unsigned long) of_claim(claim_base, size, 0); in of_try_claim()
43 if (addr == 0) in of_try_claim()
78 if (a1 && a2 && a2 != 0xdeadbeef) { in of_platform_init()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/
H A Dsdram-rv1126-lpddr3-detect-784.inc4 .rank = 0x1,
5 .col = 0xC,
6 .bk = 0x3,
7 .bw = 0x1,
8 .dbw = 0x0,
9 .row_3_4 = 0x0,
10 .cs0_row = 0x10,
11 .cs1_row = 0x10,
12 .cs0_high16bit_row = 0x10,
13 .cs1_high16bit_row = 0x10,
[all …]
H A Dsdram-rv1126-lpddr4-detect-784.inc4 .rank = 0x1,
5 .col = 0xB,
6 .bk = 0x3,
7 .bw = 0x1,
8 .dbw = 0x1,
9 .row_3_4 = 0x0,
10 .cs0_row = 0x11,
11 .cs1_row = 0x11,
12 .cs0_high16bit_row = 0x0,
13 .cs1_high16bit_row = 0x0,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
46 reg = <0x00040000 0x00040000>;
52 reg = <0x00080000 0x00700000>;
58 reg = <0x00800000 0x01400000>;
66 reg = <0x01f00000 0x00100000>;
72 ifc_nand: nand@1,0 {
76 reg = <0x1 0x0 0x10000>;
79 cpld@3,0 {
83 reg = <0x3 0x0 0x0000020>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_qe.h21 #define QE_DATAONLY_BASE 0
38 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
39 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
40 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
41 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
51 #define QE_CR_FLG 0x00010000
52 #define QE_RESET 0x80000000
53 #define QE_INIT_TX_RX 0x00000000
54 #define QE_INIT_RX 0x00000001
55 #define QE_INIT_TX 0x00000002
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dyosemite.dts19 dcr-parent = <&{/cpus/cpu@0}>;
32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0x00000000>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Deiger.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
[all …]
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/include/video/
H A Dnewport.h34 #define DM1_PLANES 0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
[all …]
/OK3568_Linux_fs/kernel/sound/firewire/fireface/
H A Dff-protocol-former.c12 #define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
14 #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
15 #define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
24 { 32000, 0x00000002, }, in parse_clock_bits()
25 { 44100, 0x00000000, }, in parse_clock_bits()
26 { 48000, 0x00000006, }, in parse_clock_bits()
27 { 64000, 0x0000000a, }, in parse_clock_bits()
28 { 88200, 0x00000008, }, in parse_clock_bits()
29 { 96000, 0x0000000e, }, in parse_clock_bits()
30 { 128000, 0x00000012, }, in parse_clock_bits()
[all …]
/OK3568_Linux_fs/u-boot/include/linux/
H A Dimmap_qe.h17 #define QE_MURAM_SIZE 0xc000UL
21 #define QE_MURAM_SIZE 0x4000UL
28 #define QE_MURAM_SIZE 0x6000UL
34 #define QE_IMMR_OFFSET 0x00140000
36 #define QE_IMMR_OFFSET 0x01400000
43 u8 res0[0x4];
45 u8 res1[0x70];
61 u8 res0[0x4];
64 u8 res1[0x4];
66 u8 res2[0x20];
[all …]
/OK3568_Linux_fs/kernel/include/soc/fsl/qe/
H A Dqe.h32 #define MEM_PART_SYSTEM 0
38 QE_CLK_NONE = 0,
136 return 0; in cpm_muram_dma()
228 return 0; in qe_alive_during_sleep()
287 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
300 __be32 traps[16]; /* Trap addresses, 0 == ignore */
344 #define BD_STATUS_MASK 0xffff0000
345 #define BD_LENGTH_MASK 0x0000ffff
353 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
354 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
[all …]
/OK3568_Linux_fs/kernel/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Ds626.h36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
39 #define S626_EOPL 0x80 /* End of ADC poll list marker. */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
44 #define S626_ERR_ILLEGAL_PARM 0x00010000 /*
48 #define S626_ERR_I2C 0x00020000 /* I2C error. */
49 #define S626_ERR_COUNTERSETUP 0x00200000 /*
53 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
74 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dhndpmu.c241 /* But 0 is a valid resource number! */
242 #define NO_SUCH_RESOURCE 0 /**< means: chip does not have such a PMU resource */
245 #define PMU_PLL_CTRL_REG0 0
265 #define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_MASK 0x1
268 #define OTP_XTAL_BIAS_VAL_4378_WRD_SHIFT 0
269 #define OTP_XTAL_BIAS_VAL_4378_WRD_MASK 0xFF
272 /* changes the drive strength of gpio_12 and gpio_14 from 0x3 to 0x01 */
273 #define GPIO_DRIVE_4378_MASK 0x3Fu
274 #define GPIO_DRIVE_4378_VAL 0x09u
382 ASSERT(0); in BCMRAMFN()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dhndpmu.c241 /* But 0 is a valid resource number! */
242 #define NO_SUCH_RESOURCE 0 /**< means: chip does not have such a PMU resource */
245 #define PMU_PLL_CTRL_REG0 0
265 #define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_MASK 0x1
268 #define OTP_XTAL_BIAS_VAL_4378_WRD_SHIFT 0
269 #define OTP_XTAL_BIAS_VAL_4378_WRD_MASK 0xFF
272 /* changes the drive strength of gpio_12 and gpio_14 from 0x3 to 0x01 */
273 #define GPIO_DRIVE_4378_MASK 0x3Fu
274 #define GPIO_DRIVE_4378_VAL 0x09u
382 ASSERT(0); in BCMRAMFN()
[all …]