Lines Matching +full:0 +full:x01400000
17 #define QE_MURAM_SIZE 0xc000UL
21 #define QE_MURAM_SIZE 0x4000UL
28 #define QE_MURAM_SIZE 0x6000UL
34 #define QE_IMMR_OFFSET 0x00140000
36 #define QE_IMMR_OFFSET 0x01400000
43 u8 res0[0x4];
45 u8 res1[0x70];
61 u8 res0[0x4];
64 u8 res1[0x4];
66 u8 res2[0x20];
68 u8 res3[0x1C];
76 u8 res0[0xA];
78 u8 res1[0x2];
83 u8 res2[0x8];
87 u8 res3[0x2];
88 u8 res4[0x24];
90 u8 res5[0x2];
92 u8 res6[0x2];
94 u8 res7[0x2];
96 u8 res8[0x2];
98 u8 res9[0x2];
100 u8 res10[0x2];
102 u8 res11[0x2];
104 u8 res12[0x2];
105 u8 res13[0x280];
119 u8 res0[0x1C];
125 u8 res0[0x3];
127 u8 res1[0xB];
149 u8 res2[0x46];
170 u8 res0[0x40];
175 u8 res0[0x20];
177 u8 res1[0x2];
179 u8 res2[0x1];
180 u8 res3[0x2];
182 u8 res4[0x1];
183 u8 res5[0x1];
185 u8 res6[0x2];
188 u8 res7[0x8];
198 u8 res0[0x1];
200 u8 res2[0x1];
202 u8 res3[0x1];
212 u8 res4[0x8];
218 u8 res5[0x1];
220 u8 res6[0x1];
222 u8 res7[0x1];
232 u8 res8[0x8];
235 u8 res9[0xBB];
240 u8 tx[0x400];
241 u8 rx[0x400];
242 u8 res0[0x800];
264 u8 res6[0x22];
273 u8 res0[0xF0];
281 u8 res0[0x2];
285 u8 res1[0x2];
287 u8 res2[0x1];
289 u8 res3[0x24];
292 u8 res4[0x200 - 0x091];
311 u8 res1[0x10];
322 u8 res2[0x8];
326 u8 res3[0x180 - 0x15A];
356 u8 res4[0x2];
377 u8 res5[0x200 - 0x1c4];
385 u8 res0[0x2];
387 u8 res1[0x2];
391 u8 res2[0x7];
394 u8 res3[0x2];
400 u8 res4[0x2];
402 u8 res5[0x2];
404 u8 res6[0x2];
406 u8 res7[0x2];
408 u8 res8[0x4C];
410 u8 res9[0x100 - 0x091];
416 u8 res1[0x90];
418 u8 res2[0x200 - 0x091];
440 u8 res0[0xC];
461 u8 res1[0x8];
462 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
466 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
470 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
474 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
482 u8 res2[0x150];
497 u8 res0[0x10];
500 u8 res1[0x4];
502 u8 res2[0x38];
510 u32 bprmrr0; /* Breakpoint request mode risc register 0 */
512 u8 res0[0x8];
513 u32 bprmtr0; /* Breakpoint request mode trb register 0 */
515 u8 res1[0x8];
519 u8 res2[0x48];
554 u8 res4[0x100-0xf8];
563 spi_t spi[0x2]; /* spi */
568 u8 res11[0x800];
574 u8 res12[0x600];
580 u8 res13[0x600];
584 rsp_t rsp[0x2]; /* RISC Special Registers
586 u8 res14[0x300];
587 u8 res15[0x3A00];
588 u8 res16[0x8000]; /* 0x108000 - 0x110000 */